Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

7.5.2. Fractional PLL Recalibration

Follow these steps to recalibrate the fPLL:

  1. Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0].
  2. Wait for reconfig_waitrequest to be deasserted (logic low) or wait until capability register of PreSICE Avalon® memory-mapped interface control 0x280[2]=0x0.
  3. To calibrate the fPLL, Read-Modify-Write 0x1 to bit[1] of address 0x100 of the fPLL.
  4. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0].