Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.7.2.2.2. Rate Switch

This section provides an overview of auto rate change between PIPE Gen1 (2.5 Gbps), Gen2 (5.0 Gbps), and Gen3 (8.0 Gbps) modes.
In Arria 10 devices, there is one ASN block common to the Standard PCS and Gen3 PCS, located in the PMA PCS interface that handles all PIPE speed changes. The PIPE interface clock rate is adjusted to match the data throughput when a rate switch is requested.
PIPE Gen3 32 bit PCS Clock Rates
PCIe* Gen3 Capability Mode Enabled Gen1 Gen2 Gen3
Lane data rate 2.5 Gbps 5 Gbps 8 Gbps
PCS clock frequency 250 MHz 500 MHz 250 MHz
FPGA fabric IP clock frequency 62.5 MHz 125 MHz 250 MHz
PIPE interface width 32-bit 32-bit 32-bit
pipe_rate [1:0] 2'b00 2'b01 2'b10
Rate Switch ChangeThe block-level diagram below shows a high level connectivity between ASN and Standard PCS and Gen3 PCS.


The sequence of speed change between Gen1, Gen2, and Gen3 occurs as follows:

  1. The PHY-MAC layer implemented in FPGA fabric requests a rate change through pipe_rate[1:0].
  2. The ASN block waits for the TX FIFO to flush out data. Then the ASN block asserts the PCS reset.
  3. The ASN asserts the clock shutdown signal to the Standard PCS and Gen3 PCS to dynamically shut down the clock.
  4. When the rate changes to or from the Gen3 speed, the ASN asserts the clock and data multiplexer selection signals.
  5. The ASN uses a pipe_sw[1:0] output signal to send a rate change request to the PMA.
  6. The ASN continuously monitors the pipe_sw_done[1:0] input signal from the PMA.
  7. After the ASN receives the pipe_sw_done[1:0] signal, it deasserts the clock shut down signals to release the clock.
  8. The ASN deasserts the PCS reset.
  9. The ASN sends the speed change completion to the PHY-MAC interface. This is done through the pipe_phy_status signal to PHY-MAC interface.
Speed Change Sequence


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