Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

1.1.5. Arria® 10 SX Device Package Details

The following tables list package sizes, available transceiver channels, and PCI Express* Hard IP blocks for Arria® 10 SX devices.
Table 5.  Package Details for SX Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device
  • Package U19: 19mm x 19mm package; 484 pins.
  • Package F27: 27mm x 27mm package; 672 pins.
  • Package F29: 29mm x 29mm package; 780 pins.
  • Packages F34 and F35: 35 mm x 35 mm package size; 1152 pins.
  • Package F40: 40 mm x 40 mm package size; 1517 pins. K = 36 transceiver channels, N = 48 transceiver channels.
Device U19 F27 F29 F34 F35 K F40 N F40
Transceiver Count, PCIe* Hard IP Block Count
SX 016 6, 1 12, 1 12, 1
SX 022 6, 1 12, 1 12, 1
SX 027 12, 1 12, 1 24, 2 24, 2
SX 032 12, 1 12, 1 24, 2 24, 2
SX 048 12, 1 24, 2 36, 2
SX 057 24, 2 36, 2 36, 2 48, 2
SX 066 24, 2 36, 2 36, 2 48, 2

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