Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.5.3. How to Implement Interlaken in Arria 10 Transceivers

You should be familiar with the Interlaken protocol, Enhanced PCS and PMA architecture, PLL architecture, and the reset controller before implementing the Interlaken protocol PHY layer.

Arria 10 devices provide three preset variations for Interlaken in the IP Parameter Editor:

  • Interlaken 10x12.5 Gbps
  • Interlaken 1x6.25 Gbps
  • Interlaken 6x10.3 Gbps
  1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog (Installed IP > Library > Interface Protocols > Transceiver PHY > Arria 10 Transceiver Native PHY).
    Refer to Select and Instantiate the PHY IP Core for more details.
  2. Select Interlaken from the Transceiver configuration rules list located under Datapath Options, depending on which protocol you are implementing.
  3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for Interlaken Transceiver Configuration Rules. Or you can use the protocol presets described in Transceiver Native PHY Presets. You can then modify the settings to meet your specific requirements.
  4. Click Generate to generate the Native PHY IP (this is your RTL file).
    Figure 38. Signals and Ports of Native PHY IP for Interlaken
  5. Configure and instantiate your PLL.
  6. Create a transceiver reset controller. You can use your own reset controller or use the Transceiver PHY Reset Controller.
  7. Implement a TX soft bonding logic and an RX multi-lane alignment deskew state machine using fabric logic resources for multi-lane Interlaken implementation.
  8. Connect the Native PHY IP to the PLL IP and the reset controller.
    Figure 39. Connection Guidelines for an Interlaken PHY Design

    This figure shows the connection of all these blocks in the Interlaken PHY design example available on the Intel® FPGA Wiki website.

    For the blue blocks, Intel provides an IP core. The gray blocks use the TX soft bonding logic that is included in the design example. The white blocks are your test logic or MAC layer logic.

  9. Simulate your design to verify its functionality.
    Figure 40.  24 Lanes Bonded Interlaken Link, TX Direction To show more details, three different time segments are shown with the same zoom level.

    24 lanes bonded Interlaken link, TX direction

    Figure 41.  24 Lanes Bonded Interlaken Link, RX Direction To show more details, three different time segments are shown with different zoom level.

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