Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents Word Aligner Manual Mode

To use this mode:

  1. Set the RX word aligner mode to Manual (FPGA Fabric controlled).
  2. Set the RX word aligner pattern length option according to the PCS-PMA interface width.
  3. Enter a hexadecimal value in the RX word aligner pattern (hex) field.

This mode adds rx_patterndetect and rx_syncstatus. You can select the Enable rx_std_wa_patternalign port option to enable rx_std_wa_patternalign. An active high on rx_std_wa_patternalign re-aligns the word aligner one time.

  • rx_patterndetect is asserted whenever there is a pattern match.
  • rx_syncstatus is asserted after the word aligner achieves synchronization.
  • rx_std_wa_patternalign is asserted to re-align and resynchronize.
  • If there is more than one channel in the design, rx_patterndetect, rx_syncstatus and rx_std_wa_patternalign become buses in which each bit corresponds to one channel.

You can verify this feature by monitoring rx_parallel_data.

The following timing diagrams demonstrate how to use the ports and show the relationship between the various control and status signals. In the top waveform, rx_parallel_data is initially misaligned. After asserting the rx_std_wa_patternalign signal, it becomes aligned. The bottom waveform shows the behavior of the rx_syncstatus signal when rx_parallel_data is already aligned.

Figure 132. Manual Mode when the PCS-PMA Interface Width is 8 Bits tx_parallel_data = 8'hBC and the word aligner pattern = 8'hBC

In manual alignment mode, the word alignment operation is manually controlled with the rx_std_wa_patternalign input signal or the rx_enapatternalign register. The word aligner operation is level-sensitive to rx_enapatternalign. The word aligner asserts the rx_syncstatus signal for one parallel clock cycle whenever it re-aligns to the new word boundary.

Figure 133. Manual Mode when the PCS-PMA Interface Widt