Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

3.5. FPGA Fabric-Transceiver Interface Clocking

The FPGA fabric-transceiver interface consists of clock signals from the FPGA fabric into the transceiver and clock signals from the transceiver into the FPGA fabric. These clock signals use the global (GCLK), regional (RCLK), and periphery (PCLK) clock networks in the FPGA core. If the Global Signal is set to Off, it does not choose any of the previously mentioned clock networks. Instead, it chooses directly from the local routing between transceiver and FPGA fabric.

The transmitter channel forwards a parallel output clock tx_clkout to the FPGA fabric to clock the transmitter data and control signals. The receiver channel forwards a parallel output clock rx_clkout to the FPGA fabric to clock the data and status signals from the receiver into the FPGA fabric. Based on the receiver channel configuration, the parallel output clock is