Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents TX Data Bitslip

The bit slip feature in the TX gearbox allows you to slip the transmitter bits before they are sent to the serializer.

The value specified on the TX bit slip bus indicates the number of bit slips. The minimum slip is one UI. The maximum number of bits slipped is equal to the FPGA fabric-to-transceiver interface width minus 1. For example, if the FPGA fabric-to-transceiver interface width is 64 bits, the bit slip logic can slip a maximum of 63 bits. Each channel has 6 bits to determine the number of bits to slip. The TX bit slip bus is a level-sensitive port, so the TX serial data is bit slipped statically by TX bit slip port assignments. Each TX channel has its own TX bit slip assignment and the bit slip amount is relative to the other TX channels. You can improve lane-to-lane skew by assigning TX bit slip ports with proper values.

The following figure shows the effect of slipping tx_serial_data[0] by one UI to reduce the skew with tx_serial_data[1]. After the bit slip, tx_serial_data[0] and tx_serial_data[1] are aligned.

Figure 128. TX Bit Slip

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