18.104.22.168. Design Example
The MAC and PHY design example instantiates the 1G/10GbE PHY IP along with the 1G/10G Ethernet MAC and supporting logic. It is part of the Intel® Quartus® Prime software installation and is located in the <quartus_install_dir>/<version_number>/ip/altera/ethernet subdirectory. For more information about this example design, refer to the Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide .
A design example that instantiates the 1G/10G PHY and its supporting logic is available on the Intel® FPGA wiki. The following figure shows the block diagram of the 1G/10GbE PHY-only design example. The default configuration includes two channels for backplane Ethernet and two channels for line-side (1G/10G) applications.