Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic with KR FEC

This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.

Table 211.  General and Datapath ParametersThe first two sections of the Parameter Editor for the Transceiver Native PHY provide a list of general and datapath options to customize the transceiver.

Parameter

Range

Message level for rule violations

error, warning

Transceiver configuration rules

Basic (Enhanced PCS), Basic w/KR FEC

PMA configuration rules

Basic, QPI, GPON

Transceiver mode

TX / RX Duplex, TX Simplex, RX Simplex

Number of data channels

1 to 96

Data rate

GX transceiver channel: 1 Gbps 49 to 17.4 Gbps

GT transceiver channel: 1 Gbps 49 to 25.8 Gbps 50

Enable datapath and interface reconfiguration

On / Off

Enable simplified data interface

On / Off

Table 212.  TX PMA Parameters

Parameter

Range

TX channel bonding mode

Not bonded, PMA only bonding, PMA and PCS bonding

PCS TX channel bonding master

Auto, 0 to n-1, n (where n = the number of data channels)

Actual PCS TX channel bonding master

n-1 (where n = the number of data channels)

TX local clock division factor

1, 2, 4, 8

Number of TX PLL clock inputs per channel

1, 2, 3, 4

Initial TX PLL clock input selection

0

Enable tx_pma_clkout port On / Off
Enable tx_pma_div_clkout port On / Off
tx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port On / Off
Enable tx_pma_qpipullup port (QPI) On / Off
Enable tx_pma_qpipulldn port (QPI) On / Off
Enable tx_pma_txdetectrx port (QPI) On / Off
Enable tx_pma_rxfound port (QPI) On / Off
Enable rx_serialpbken port On / Off
Table 213.  RX PMA Parameters

Parameter

Range

Number of CDR reference clocks

1 to 5

Selected CDR reference clock

0 to 4

Selected CDR reference clock frequency

For Basic (Enhanced PCS): Depends on the data rate parameter

For Basic with KR FEC: 50 to 800

PPM detector threshold

100, 300, 500, 1000

CTLE adaptation mode

manual

DFE adaptation mode

adaptation enabled, manual, disabled

Number of fixed dfe taps

3, 7

Enable rx_pma_clkout port On / Off
Enable rx_pma_div_clkout port On / Off
rx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable rx_pma_clkslip port On / Off
Enable rx_pma_qpipulldn port (QPI) On / Off
Enable rx_is_lockedtodata port On / Off
Enable rx_is_lockedtoref port On / Off
Enable rx_set_locktodata and rx_set_locktoref ports On / Off
Enable rx_serialpbken port On / Off
Enable PRBS verifier control and status ports On / Off
Table 214.  Enhanced PCS Parameters

Parameter

Range

Enhanced PCS/PMA interface width

32, 40, 64

Note: Basic with KR FEC allows 64 only

FPGA fabric/Enhanced PCS interface width

32, 40, 50, 64, 66, 67

Note: Basic with KR FEC allows 66 only

Enable Enhanced PCS low latency mode

On / Off

Enable RX/TX FIFO double width mode

On / Off

TX FIFO mode

Phase compensation, Register, Interlaken, Basic, Fast register

Note: Only Basic Enhanced and Basic Enhanced with KRFEC are valid.

TX FIFO partially full threshold

10, 11, 12, 13, 14, 15

TX FIFO partially empty threshold

1, 2, 3, 4, 5

Enable tx_enh_fifo_full port

On / Off

Enable tx_enh_fifo_pfull port

On / Off

Enable tx_enh_fifo_empty port

On / Off

Enable tx_enh_fifo_pempty port

On / Off

RX FIFO mode

Phase Compensation, Register, Basic

RX FIFO partially full threshold

0 to 31

RX FIFO partially empty threshold

0 to 31

Enable RX FIFO alignment word deletion (Interlaken)

On / Off

Enable RX FIFO control word deletion (Interlaken)

On / Off

Enable rx_enh_data_valid port

On / Off

Enable rx_enh_fifo_full port

On / Off

Enable rx_enh_fifo_pfull port

On / Off

Enable rx_enh_fifo_empty port

On / Off

Enable rx_enh_fifo_pempty port

On / Off

Enable rx_enh_fifo_del port (10GBASE-R)

On / Off

Enable rx_enh_fifo_insert port (10GBASE-R)

On / Off

Enable rx_enh_fifo_rd_en port (Interlaken)

On / Off

Enable rx_enh_fifo_align_val port (Interlaken)

On / Off

Enable rx_enh_fifo_align_cir port (Interlaken)

On / Off

Enable TX 64b/66b encoder

On / Off

Enable RX 64b/66b decoder

On / Off

Enable TX sync header error insertion

On / Off

Enable RX block synchronizer

On / Off

Enable rx_enh_blk_lock port

On / Off

Enable TX data bitslip

On / Off

Enable TX data polarity inversion

On / Off

Enable RX data bitslip

On / Off

Enable RX data polarity inversion

On / Off

Enable tx_enh_bitslip port

On / Off

Enable rx_bitslip port

On / Off

Enable RX KR-FEC error marking

On / Off

Error marking type

10G, 40G

Enable KR-FEC TX error insertion

On / Off

KR-FEC TX error insertion spacing

On / Off

Enable tx_enh_frame port

On / Off

Enable rx_enh_frame port

On / Off

Enable rx_enh_frame_dian_status port

On / Off

Table 215.  Dynamic Reconfiguration Parameters
Parameter Range
Enable dynamic reconfiguration

On / Off

Share reconfiguration interface

On / Off

Enable Native PHY Debug Master Endpoint

On / Off

Enable embedded debug

On / Off

Enable capability registers

On / Off

Set user-defined IP identifier number
Enable control and status registers

On / Off

Enable prbs soft accumulators

On / Off

Configuration file prefix text string
Generate SystemVerilog package file

On / Off

Generate C header file

On / Off

Table 216.  Generate Options Parameters
Parameter Range
Generate parameter documentation file

On / Off

49 Applies when operating in reduced power modes. For standard power modes, the Enhanced PCS minimum data rate is 1600 Mbps.
50 The Enhanced PCS must be configured in basic mode to support this data rate range.

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