Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.4.7.6. Speed Change Summary

Table 149.  Speed Change Summary
Speed Change Speed Change Method Detailed Information
1GbE and 10GBASE-R Interface Signals
SGMII (10M, 100M and 1GbE) Avalon® memory-mapped interface bus Enhanced PCS Registers
1GbE, 10GBASE-R, and 10GBASE-R with FEC Avalon® memory-mapped interface bus 1G/10GbE Register Definitions
Note: You can configure the static speed while generating the IP core using the IP Parameter Editor.

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