Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.6.5.5.4. XGMII Signals

The XGMII supports 10GbE at 156.25 MHz.

Table 163.  XGMII Signals
Signal Name Direction Width Description
TX XGMII signals—synchronous to xgmii_tx_coreclkin
xgmii_tx_data

Input

64, 32

TX data from the MAC. The MAC sends the data in the following order: bits[7:0], bits[15:8], and so forth.

The width is:
  • 64 bits for 1G/2.5G/10G configurations.
  • 32 bits for 10M/100M/1G/2.5G/5G/10G configurations.
xgmii_tx_control

Input

8, 4
TX control from the MAC:
  • xgmii_tx_control[0] corresponds to xgmii_tx_data[7:0]
  • xgmii_tx_control[1] corresponds to xgmii_tx_data[15:8]
  • and so forth.
The width is:
  • 8 bits for 1G/2.5G/10G configurations.
  • 4 bits for 10M/100M/1G/2.5G/5G/10G configurations.
xgmii_tx_valid Input 1 Indicates valid data on xgmii_tx_control and xgmii_tx_data from the MAC.
Your logic/MAC must toggle the valid data as shown below:
Speed Toggle Rate
10M Asserted once every 1000 clock cycles
100M Asserted once every 100 clock cycles
1G Asserted once every 10 clock cycles
2.5G Asserted once every 4 clock cycles
5G Asserted once every 2 clock cycles
10G Asserted in every clock cycle
RX XGMII signals—synchronous to xgmii_rx_coreclkin
xgmii_rx_data Output 64, 32

RX data to the MAC. The PHY sends the data in the following order: bits[7:0], bits[15:8], and so forth.

The width is:
  • 64 bits for 1G/2.5G/10G configurations.
  • 32 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.
xgmii_rx_control Output 8, 4 RX control to the MAC.
  • xgmii_rx_control[0] corresponds to xgmii_rx_data[7:0]
  • xgmii_rx_control[1] corresponds to xgmii_rx_data[15:8]
  • and so forth.
The width is:
  • 8 bits for 1G/2.5G/10G configurations.
  • 4 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.
xgmii_rx_valid Output 1 Indicates valid data on xgmii_rx_control and xgmii_rx_data from the MAC.
The toggle rate from the PHY is shown in the table below.
Note: The toggle rate may vary when the start of a packet is received or when rate match occurs inside the PHY. You should not expect the valid data pattern to be fixed.
Speed Toggle Rate
10M Asserted every 1000 clock cycles
100M Asserted every 100 clock cycles
1G Asserted once every 10 clock cycles
2.5G Asserted once every 4 clock cycles
5G Asserted once every 2 clock cycles
10G Asserted in every clock cycle

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