Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.4.4. Clock and Reset Interfaces

You can use a fPLL or a CMU PLL to generate the clock for the TX PMA for the 1G data rate. For the 10G data rate, you can use the ATX PLL or the CMU PLL. For the 1G data rate, the frequency of the TX and RX clocks is 125 MHz, which is 1/8 of the MAC data rate. For the 10G data rate, the frequency of TX and RX clocks is 156.25 MHz, 1/64 of the MAC data rate. You can generate the 156.25 MHz clock directly by using a fPLL, or you can divide the clock from TX PLL by 33. The 1G/10GbE PHY does not support bonded clocks.

The following figure provides an overview of the clocking for this core.

Figure 75.  Clocks for Standard and 10G PCS and TX PLLs

The following table describes the clock and reset signals.

Table 128.  Clock and Reset Signals
Signal Name Direction Description
tx_serial_clk_10g Input High speed clock from the 10G PLL to drive 10G PHY TX PMA. The frequency of this clock is 5.15625 GHz.
tx_serial_clk_1g Input The clock from the external 1G PLL to drive the TX high speed serial interface (HSSI) circuits. Connected to the tx_serial_clk input of the native PHY.
rx_cdr_ref_clk_10g Input 10G PHY RX PLL reference clock. This clock frequency can be 644.53125 MHz or 322.2656 MHz.
rx_cdr_refclk_1g Input The RX 1G PLL reference clock to drive the RX HSSI circuits. Connected to the rx_cdr_refclk input of the native PHY.
mgmt_clk Input Avalon® memory-mapped interface clock and control system clock. Its frequency range is 100 MHz to 125 MHz.
mgmt_clk_reset Input When asserted, it resets the whole PHY.
xgmii_tx_clk Input Clock for XGMII TX interface with MAC. Can be connected to tx_div_clkout. This drives the tx_coreclkin port of the Native PHY.
xgmii_rx_clk Input The clock for the XGMII RX interface with the MAC. Intel recommends connecting it directly to a PLL for use with TSE. This drives rx_coreclkin of the native PHY. Its frequency is 156.25 or 312.5 MHz.
tx_clkout Output Transmit parallel clock. It is sourced from out_pld_pcs_tx_clk_out on the HSSI. This could be used to provide the XGMII clocks or the GMII clocks, though if the PHY is reconfigured, the frequency changes. Its frequency is 125, 156.25, 161, 258, or 312.5 MHz.
rx_clkout Output Receive parallel clock. It is sourced from out_pld_pcs_rx_clk_out on the HSSI. If the PHY is reconfigured, the frequency changes. Its frequency is 125, 156.25, 161, 258, or 312.5 MHz.
tx_pma_clkout Output Transmit PMA clock. This is the clock for the 1588 mode TX FIFO and the 1G TX and RX PCS parallel data interface. Note: Use tx_div_clkout or xgmii_tx_clk for 10G TX datapath clocking. This clock is provided for the 1G mode GMII/MII data and SyncE mode where the clock can be used as a reference to lock an external clock source. Its frequency is 125, 161, or 258 MHz.
rx_pma_clkout Output Receive PMA clock. This is the clock for the 1588 mode RX FIFO and the 1G RX FIFO. Note: Use tx_div_clkout or xgmii_rx_clk for 10G RX datapath clocking. This clock is provided for the SyncE mode where the clock can be used as a reference to lock an external clock source. Its frequency is 125, 161, or 258 MHz.
tx_div_clk Output This is the transmit div33 clock, which is sourced from the Native PHY tx_pma_div_clkout. It could be connected to the xgmii_tx_clk and xgmii_rx_clk clock inputs to drive the MAC interface, though if the PHY is reconfigured to 1G mode, the frequency changes. Its frequency is 125, 156.25, or 312.5 MHz.
rx_div_clk Output This is the receive div33 clock, which is recovered from the received data. It drives the Auto Negotiation (AN) and Link Training (LT) logic and is sourced from the Native PHY rx_pma_div_clkout port. Note: Use tx_clkout or xgmii_rx_clk for 10G TX datapath clocking. If the PHY is reconfigured to 1G mode, the frequency changes. Its frequency is 125, 156.25, or 312.5 MHz.
calc_clk_1g Input

This is the clock for the GIGE PCS 1588 mode. To achieve high accuracy for all speed modes, the recommended frequency for calc_clk_1g is 80 MHz. In addition, the 80 MHz clock should have the same parts per million (ppm) as the 125 MHz pll_ref_clk_1g input. The random error without a rate match FIFO mode is:

  • ±1 ns at 1000 Mbps
  • ± 5 ns at 100 Mbps
  • ± 25 ns at 10 Mbps
tx_analogreset Input Resets the analog TX portion of the transceiver PHY. Synchronous to mgmt_clk.
tx_digitalreset Input Resets the digital TX portion of the transceiver PHY. Synchronous to mgmt_clk.
rx_analogreset Input Resets the analog RX portion of the transceiver PHY. Synchronous to mgmt_clk.
rx_digitalreset Input Resets the digital RX portion of the transceiver PHY. Synchronous to mgmt_clk.
usr_seq_reset Input Resets the sequencer. Initiates a PCS reconfiguration, and may restart AN, LT or both if these modes are enabled. Synchronous to mgmt_clk.
rx_data_ready Output When asserted, indicates that you can start to send the 10G data. Synchronous to xgmii_rx_clk.

Did you find the information on this page useful?

Characters remaining:

Feedback Message