18.104.22.168. Clock and Reset Interfaces
You can use a fPLL or a CMU PLL to generate the clock for the TX PMA for the 1G data rate. For the 10G data rate, you can use the ATX PLL or the CMU PLL. For the 1G data rate, the frequency of the TX and RX clocks is 125 MHz, which is 1/8 of the MAC data rate. For the 10G data rate, the frequency of TX and RX clocks is 156.25 MHz, 1/64 of the MAC data rate. You can generate the 156.25 MHz clock directly by using a fPLL, or you can divide the clock from TX PLL by 33. The 1G/10GbE PHY does not support bonded clocks.
The following figure provides an overview of the clocking for this core.
The following table describes the clock and reset signals.
|tx_serial_clk_10g||Input||High speed clock from the 10G PLL to drive 10G PHY TX PMA. The frequency of this clock is 5.15625 GHz.|
|tx_serial_clk_1g||Input||The clock from the external 1G PLL to drive the TX high speed serial interface (HSSI) circuits. Connected to the tx_serial_clk input of the native PHY.|
|rx_cdr_ref_clk_10g||Input||10G PHY RX PLL reference c|