Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.9.1.1. How to Implement the Basic (Enhanced PCS) and Basic with KR FEC Transceiver Configuration Rules in Arria 10 Transceivers

You should be familiar with the Basic (Enhanced PCS) and PMA architecture, PLL architecture, and the reset controller before implementing the Basic (Enhanced PCS) or Basic with KR FEC Transceiver Configuration Rule.

  1. Open the IP Catalog and select the Arria 10 Transceiver Native PHY IP.
    Refer to Select and Instantiate the PHY IP Core for more details.
  2. Select Basic (Enhanced PCS) or Basic with KR FEC from the Transceiver Configuration Rules list located under Datapath Options.
  3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for Basic (Enhanced PCS) and Basic with KR FEC Transceiver Configuration Rules as a starting point. Or, you can use the protocol presets described in Transceiver Native PHY Presets. You can then modify the settings to meet your specific requirements.
  4. Click Finish to generate the Native PHY IP (this is your RTL file).
    Figure 123. Signals and Ports of Native PHY IP for Basic (Enhanced PCS) and Basic with KR FEC Configurations
  5. Configure and instantiate the PLL.
  6. Create a transceiver reset controller. You can use your own reset controller or use the Transceiver PHY Reset Controller.
  7. Connect the Native PHY IP core to the PLL IP core and the reset controller.
    Figure 124. Connection Guidelines for a Basic (Enhanced PCS) Transceiver Design
    Figure 125. Connection Guidelines for a Basic with KR FEC Transceiver Design


  8. Simulate your design to verify its functionality.

Did you find the information on this page useful?

Characters remaining:

Feedback Message