Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.9.3.4. How to Implement Designs for Data Rates Above 17.4 Gbps Using Enhanced PCS in Low Latency Mode

  • You should be familiar with the Enhanced PCS and PMA architecture, PLL architecture, and the reset controller.
  • Make sure you have selected an Arria 10 GT device for the project
  1. Select Tools > IP Catalog > Interface Protocols > Transceiver PHY > Arria 10 Transceiver Native PHY. Refer to Select and Instantiate the PHY IP Core for detailed steps.
  2. Set VCCR_GXB and VCCT_GXB to 1.1V. Note these settings are overridden by the QSF file settings which should also be set to 1.1V. QII makes sure the actual voltage prescribed is in line with pin connection guidelines and the Arria10 Data Sheet.
  3. Select Basic (Enhanced PCS) from the Transceiver configuration rules list located under Datapath Options.
  4. Use the parameter values in the tables in Transceiver Native PHY IP Parameters Settings for Basic (Enhanced PCS) and Basic with KR FEC for each input of the Arria 10 Transceiver Native PHY Parameter Editor as a starting point. Or, you can use the protocol presets described in Transceiver Native PHY Presets. You can then modify the settings to meet your specific requirements.
    • Ensure that the data rate is set to 25781.25 Mbps. To achieve the higher data rates, use Enhanced PCS basic mode with the low latency option unchecked. Select a CDR reference clock to match your data rate. Use Phase compensation FIFO modes.
    • Make sure DFE is disabled from Rx PMA settings.
    • Set the Enhanced PCS / PMA interface width to 64 bits.
    • Set the FPGA fabric / Enhanced PCS interface width to 64 bits.
    • You can enable RX/TX FIFO double width mode to create a FPGA fabric / PCS interface width of 128 bits.
    • Click Finish to generate the Native PHY IP (this is your RTL file).
    Figure 162. Signals and Ports of the Native PHY for Basic (Enhanced PCS) Transceiver Configuration Rule for Data Rates Above 17.4 Gbps and FPGA Fabric / PCS Interface width of 128 bits


  5. Select Tools > IP Catalog > Basic Functions > Clocks > PLLs and Resets > PLL > Arria 10 Transceiver ATX PLL. Refer to Instantiating the ATX PLL IP Core for detailed steps.
  6. Configure the ATX PLL IP using the Parameter Editor.
    • Select the GT clock output buffer.
    • Enable the PLL GT clock output port.
    • Set the PLL output clock frequency to the Native PHY IP recommended frequency.
    Figure 163. ATX PLL IP with GT Clock Lines Enabled
  7. Create a transceiver reset controller. Refer to Resetting Transceiver Channels for more details about configuring the reset IP core.
  8. Connect the Native PHY IP core to the PLL IP core and the reset controller.

    The ATX PLL's port tx_serial_clk_gt represents the dedicated GT clock lines. Connect this port to the Native PHY IP core's tx_serial_clk0 port. The Quartus Prime software automatically uses the dedicated GT clocks instead of the x1 clock network.

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