Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents How to Implement Designs for Data Rates Above 17.4 Gbps Using Enhanced PCS in Low Latency Mode

  • You should be familiar with the Enhanced PCS and PMA architecture, PLL architecture, and the reset controller.
  • Make sure you have selected an Arria 10 GT device for the project
  1. Select Tools > IP Catalog > Interface Protocols > Transceiver PHY > Arria 10 Transceiver Native PHY. Refer to Select and Instantiate the PHY IP Core for detailed steps.
  2. Set VCCR_GXB and VCCT_GXB to 1.1V. Note these settings are overridden by the QSF file settings which should also be set to 1.1V. QII makes sure the actual voltage prescribed is in line with pin connection guidelines and the Arria10 Data Sheet.
  3. Select Basic (Enhanced PCS) from the Transceiver configuration rules list located under Datapath Options.
  4. Use the parameter values in the tables in Transceiver Native PHY IP Parameters Settings for Basic (Enhanced PCS) and Basic with KR FEC for each input of the Arria 10 Transceiver Native PHY Parameter Editor as a starting point. Or, you can use the protocol presets described in