Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents

7.2.4. ATX PLL Calibration Registers

Table 299.  ATX PLL Calibration Registers
Bit ATX PLL Calibration Enable Register Offset Address 0x100
0 ATX PLL calibration enable. Set 1 to enable calibration.
1 Reserved

During calibration when reconfig_waitrequest is high, you cannot read or write calibration enable registers.

To enable calibration, you must perform a read-modify-write on offset address 0x100. The following steps are an example of how to enable the ATX PLL calibration enable bit:

  1. Read the offset address 0x100.
  2. Keep the value from MSB[7:1] and set LSB[0] to 1.
  3. Write new value to offset address 0x100.

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