Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents
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7.2.4. ATX PLL Calibration Registers

Table 299.  ATX PLL Calibration Registers
Bit ATX PLL Calibration Enable Register Offset Address 0x100
0 ATX PLL calibration enable. Set 1 to enable calibration.
1 Reserved

During calibration when