Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.6.3. 10GBASE-KR PHY IP Core

The 10GBASE-KR Ethernet PHY IP core supports the following features of Ethernet standards:

  • Auto negotiation for backplane Ethernet as defined in Clause 73 of the IEEE 802.3 2008 Standard. The 10GBASE-KR Ethernet PHY IP Function can auto negotiate between 1000BASE-X, 1000BASE-KR , and 1000BASE-KR with FEC.
  • 10GBASE-KR Ethernet protocol with link training as defined in Clause 72 of the IEEE 802.3 2008 Standard. In addition to the link-partner TX tuning as defined in Clause 72, this PHY also automatically configures the local device RX interface to achieve less than 10-12 bit error rate (BER) target.
  • Gigabit Media Independent Interface (GMII) to connect PHY with media access control (MAC) as defined in Clause 35 of the IEEE 802.3 2008 Standard
  • Forward Error Correction (FEC) as defined in Clause 74 of the IEEE 802.3 2008 Standard

The Backplane Ethernet 10GBASE-KR PHY IP core includes the following new modules to enable operation over a backplane:

  • Link Training (LT)— The LT mechanism allows the 10GBASE-KR PHY to automatically configure the link-partner TX PMDs for the lowest Bit Error Rate (BER). LT is defined in Clause 72 of IEEE Std 802.3ap-2007.
  • Auto negotiation (AN)—The 10GBASE-KR PHY IP core can auto-negotiate between 1000BASE-KX (1GbE) and 10GBASE-KR (10GbE) PHY types. The AN function is mandatory for Backplane Ethernet. It is defined in Clause 73 of the IEEE Std 802.3ap-2007.
  • Forward Error Correction (FEC)—FEC function is an optional feature defined in Clause 74 of IEEE 802.3ap-2007. It provides an error detection and correction mechanism.

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