Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents PRBS Soft Accumulators

The Pseudo Random Binary Sequence (PRBS) soft accumulators are used in conjunction with the hard PRBS blocks in the transceiver channel. This section describes the soft logic that can be added to the Native PHY IP core. To enable this option, turn on the Enable PRBS Soft Accumulators option in the Native PHY IP Parameter Editor.
The PRBS soft accumulator has three control bits (Enable, Reset, and Snapshot) and one status bit (PRBS Done).
  • Enable bit—used to turn on the accumulation logic. This bit is also used for selective error accumulation and to pause the sequence.
  • Reset bit—resets the PRBS polynomial and the bit and error accumulators. It also resets the snapshot registers if independent channel snapshots are used.
  • Snapshot bit—captures the current value of the accumulated bits and the errors simultaneously. This neutralizes the impact of the added read time when the Avalon® memory-mapped interface is used. Capturing a snapshot provides an accurate error count with respect to the bit count at a specific time.
  • PRBS Done bit—indicates the PRBS checker has had sufficient time to lock to the incoming pattern.

For example, to capture the accumulated errors at any instance of time and read them back, you can perform the following operations.

  1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic Reconfiguration.
  2. Perform read-modify-write to address 0x300 and set bit 0 to 1'b1. This action enables the error and bit counters.
  3. To capture the errors accumulated at a particular instant, perform read-modify-write to address 0x300 and set bit 2 to 1'b1. This takes a snapshot of the error counters and stores the value to the error count registers.
  4. To read the number of errors accumulated when the snapshot was captured, perform a read from the corresponding error registers 0x301 to 0x307.
  5. To reset the bit and error accumulators, perform a read-modify-write to address 0x300 bit 1.
  6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic Reconfiguration.
Note: You can enable the error and bit counters (0x300[0]) and capture the accumulated bits and errors at different times. The error count registers and bit count registers are updated with the latest counter values as long as the counter enable bit is set.