Visible to Intel only — GUID: nik1398707032259
Ixiasoft
Visible to Intel only — GUID: nik1398707032259
Ixiasoft
3.1.3.2. fPLL IP Core
Parameters | Range | Description |
---|---|---|
fPLL Mode |
Core Cascade Source Transceiver |
Specifies the fPLL mode of operation. Select Core to use fPLL as a general purpose PLL to drive the FPGA core clock network. Select Cascade Source to connect an fPLL to another PLL as a cascading source. Select Transceiver to use an fPLL as a transmit PLL for the transceiver block. |
Protocol Mode |
Basic PCIe* Gen1 PCIe Gen2 SDI_direct SATA TX |
Governs the internal setting rules for the VCO. This parameter is not a preset. You must set all parameters for your protocol. |
Enable fractional mode |
On/Off |
Enables the fractional frequency mode. This enables the PLL to output frequencies which are not integral multiples of the input reference clock. |