Visible to Intel only — GUID: nik1398707032259
Ixiasoft
Visible to Intel only — GUID: nik1398707032259
Ixiasoft
3.1.3.2. fPLL IP Core
Parameters | Range | Description |
---|---|---|
fPLL Mode |
Core Cascade Source Transceiver |
Specifies the fPLL mode of operation. Select Core to use fPLL as a general purpose PLL to drive the FPGA core clock network. Select Cascade Source to connect an fPLL to another PLL as a cascading source. Select Transceiver to use an fPLL as a transmit PLL for the transceiver block. |
Protocol Mode |
Basic PCIe* Gen1 PCIe Gen2 PCIe Gen3 SDI_cascade OTN_cascade SDI_direct SATA TX OTN_direct SATA_Gen3 HDMI |
Governs the internal setting rules for the VCO. This parameter is not a preset. You must set all parameters for your protocol. |
Enable fractional mode |
On/Off |
Enables the fractional frequency mode. This enables the PLL to output frequencies which are not integral multiples of the input reference clock. |
Enable physical output clock parameters |
On/Off |
Selecting this option allows you to manually specify M, N, C and L counter values. |
Enable clklow and fref ports 57 |
On/Off |
Enables fref and clklow clock ports for external lock detector. In Transceiver mode when "enable fractional mode" and "SDI_direct" prot_mode are selected, pll_locked port is not available and user can create external lock detector using fref and clklow clock ports. |
Desired Reference clock frequency |
Refer to the GUI |
Specifies the desired PLL input reference clock frequency. |
Actual reference clock frequency |
Read-only |
Displays the actual PLL input reference clock frequency. |
Number of PLL reference clocks |
1 to 5 |
Specify the number of input reference clocks for the fPLL. |
New parameter: Selected reference clock source |
0 to 4 |
Specifies the initially selected reference clock input to the fPLL. |
Bandwidth |
Low Medium High |
Specifies the VCO bandwidth. Higher bandwidth reduces PLL lock time, at the expense of decreased jitter rejection. |
Operation mode |
Direct Feedback compensation bonding |
Specifies the feedback operation mode for the fPLL. |
Multiply factor (M-counter) |
8 to 127 (integer mode) 11 to 123 (fractional mode) |
Specifies the multiply factor (M-counter). |
Divide factor (N-counter) |
1 to 31 |
Specifies the divide factor (N-counter). |
Divide factor (L-counter) |
1, 2, 4, 8 |
Specifies the divide factor (L-counter). |
Divide factor (K-counter) |
User defined |
Specifies the divide factor (K-counter). |
PLL output frequency |
Read-only |
Displays the target output frequency for the PLL. |
PLL Datarate |
Read-only |
Displays the PLL datarate. |
Parameters | Range | Description |
---|---|---|
Include Master Clock Generation Block |
On/Off |
When enabled, includes a master CGB as a part of the fPLL IP core. The PLL output drives the master CGB. This is used for x6/xN bonded and non-bonded modes. |
Clock division factor |
1, 2, 4, 8 |
Divides the master CGB clock input before generating bonding clocks. |
Enable x6/xN non-bonded high-speed clock output port |
|