Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.8.1. Transceiver Channel Datapath and Clocking for CPRI

Figure 115. Transceiver Channel Datapath and Clocking for CPRI
Table 201.  Channel Width Options for Supported Serial Data Rates
Serial Data Rate (Mbps) Channel Width (FPGA-PCS Fabric)
8/10 Bit Width 16/20 Bit Width
8-Bit 16-Bit 16-Bit 32-Bit
614.446 Yes Yes N/A N/A
1228.8 Yes Yes Yes Yes
2457.6 Yes Yes Yes Yes
3072 Yes Yes Yes Yes
4915.2 N/A N/A Yes Yes
6144 N/A N/A Yes Yes
9830.4 N/A N/A N/A Yes
Table 202.  Interface Width Options for 10.1376 Gbps and 12.16512 Gbps Data Rates
Serial Data Rate (Mbps) Interface Width
FPGA fabric - Enhanced PCS (bit) Enhanced PCS - PMA (bit)
10137.6 66 32, 40, 64
12165.12 66 40, 64
46 Over-sampling is required to implement 614.4Mbps

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