Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

6.20. Reconfiguration Interface and Dynamic Revision History

Document Version Changes
2021.06.10 Updated the Embedded Debug Features section.
2019.05.31 Made the following change:
  • Updated the link to the Arria® 10 Pre-Emphasis and Output Swing Settings tool.
2019.05.13 Made the following change:
  • Renamed Altera Debug Master Endpoint (ADME) to Native PHY DebugMaster Endpoint (NPDME).
2018.06.15 Made the following change:
  • Added instructions on how to enable the Transceiver Toolkit capability in the Native PHY IP to Dynamic Reconfiguration Parameters.
2017.11.06 Made the following changes:
  • Updated the note in "Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow" topic to "The PMA analog settings are governed by a set of rules. Not all combinations of VOD and pre-emphasis are valid. Please refer to Arria® 10 Pre-Emphasis and Output Swing Settings for current valid settings. Also, refer to "Analog Parameter Settings" and setup guidelines on post_tap polarity settings."
  • Updated the description of bit [25:16] in table "Mapping of SystemVerilog Configuration File Line" to "DPRIO address. Refer to Intel® Arria® 10 Transceiver Register Map for details of the address."
  • Changes the configurations file path to "<IP instance name>\altera_xcvr_<IP type>_a10_<quartus version>\synth\reconfig".
  • Added Examples 1 and 2 in "fPLL Reference Clock Switching" topic.
2016.10.31 Made the following changes:
  • "VGA" PMA Analog Feature added in "PMA Analog Settings that are Channel or System Dependent" table.
  • Updated the value of AC Gain Control of High Gain Mode CTLE parameter to radp_ctle_acgain_4s_0 to radp_ctle_acgain_4s_28 in the "Analog PMA Settings (Optional) for Dynamic Reconfiguration" table.
  • Updated the value of Slew Rate Control parameter to slew_r0 to slew_r5 in the "Analog PMA Settings (Optional) for Dynamic Reconfiguration" table.
2016.05.02 Made the following changes
  • Removed the topic "On-Die Instrumentation" and related information from the user guide.
  • Edited "Native PHY IP" with "Native PHY IP and ATX PLL IP" wherever necessary.
  • Edited "Embedded Reconfiguration Steamer" topic.
  • Edited the "Arbitration" topic.
  • Edited the "Using PRBS and Square Wave Data Pattern Generator and Checker" for bonded as well as non bonded designs. Also added all the examples for each case.
  • Updated "Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow" topic.
2015.12.18 Made the following changes:
  • Updated the switching bit register definitions in the “Register Map for Switching fPLL Reference Clock Inputs” table
  • Updated the “Bit Values to Be Set” table in the “Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow” section.
2015.11.02 Made the following changes:
  • Changed the procedure in the "Steps to Perform Dynamic Reconfiguration" section to be more general, allowing procedures in other sections to refer to it.
  • Added the "Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow" section.
  • Added the "Analog PMA Settings (Optional) for Dynamic Reconfiguration" table.
  • Removed four tables from the "On-Die Instrumentation" section.
  • Changed the procedure in the "Using ODI to Build On-chip Eye Process" section.
  • Added entry to “Arria 10 Dynamic Reconfiguration Feature Support” table
  • Improved description of access requests in the “Interacting with the Reconfiguration Interface” section
  • Updated the “Configuration Files” section
  • Added information to the “Embedded Reconfiguration Streamer” section
  • Modified the “Arria 10 Native PHY with Embedded Streamer” figure
  • Described the two levels of arbitration in the “Arbitration” section
  • Converted the “Steps to Perform Dynamic Reconfiguration” figure in the “Steps to Perform Dynamic Reconfiguration” section to a set of procedures
  • Added the “Reset Recommendations for Dynamic Reconfiguration” section
  • Added information about the PMA analog settings to the “Changing PMA Analog Parameters” section
  • Added steps to the procedure in the “Changing CTLE Settings in Manual Mode” section
  • Updated the steps in the procedures in the “Serial Loopback Mode” section
  • Changed title of “IP Guided Reconfiguration Flow” to “Native PHY or PLL IP Guided Reconfiguration Flow”
  • Updated the steps in the procedures in the “Native PHY or PLL IP Guided Reconfiguration Flow” and added a note following the first procedure
  • Updated the steps in the procedure in the “Switching Transmitter PLL” section
  • Updated the steps in the procedures in the “ATX Reference Clock,” “fPLL Reference Clock,” and “CDR and CMU Reference Clock,” sections
  • Updated the “Avalon Interface Parameters” table to show which parameter editors are valid for each parameter
  • Corrected values in step 1a in the “Start Pattern Checker” section
  • Added information about hard PRBS blocks to the “PRBS Soft Accumulators” section
  • Added list of PRBS checker control and status signals to the “Using PRBS and Square Wave Data Pattern Generator and Checker” section
  • Updated the steps in the procedures in the “Enabling the PRBS and Square Wave Data Generator” and the “Enabling the PRBS and Data Checker” sections
  • Updated the steps in the procedures in the “Examples of Enabling the PRBS9 and PRBS31 Pattern Generators” and the “Examples of Enabling the PRBS Data Checker” sections
  • Updated the steps in the procedure in the “Enabling Pseudo Random Pattern Mode” section
2015.05.11 Made the following changes:
  • Completely revised, updated, and reorganized the chapter.
  • Added the following new sections:
    • Multiple Reconfiguration Profiles
    • Embedded Reconfiguration Streamer
    • Arbitration
    • Enabling and Disabling Loopback Modes
    • IP Guided Reconfiguration Flow
    • On-Die Instrumentation
    • Native PHY Debug Master Endpoint
    • ODI Acceleration Logic
2014.12.15 Made the following changes:
  • Re-organized the chapter outline to better match the reconfiguration flow.
  • Updated the introduction section of the chapter to better explain dynamic reconfiguration use cases.
  • Added figures Reconfiguration Interface in Arria 10 Transceiver IP Cores and Top Level Signals of the Reconfiguration Interface.
  • Added Timing Closure Recommendations section.
  • Changed Max Vod Value in Table: PMA Analog Feature Offsets.
  • Updated Table: Valid Maximum Pre-Emphasis Settings.
  • Updated the Ports and Parameters section:
    • Updated the description to better indicate the difference between "Shared" and "Not Shared" reconfiguration interface.
    • Updated Avalon clock frequency to 100 MHz.
    • Updated the signal names in Table: Reconfiguration Interface Ports with Shared Reconfiguration Interface Enabled and Reconfiguration Interface Ports with Shared Reconfiguration Interface Disabled.
  • Added a description in Interfacing with Reconfiguration Interface section to indicate the steps to request access of the Avalon® memory-mapped interface.
  • Updated steps in Performing a Read to the Reconfiguration Interface and Performing a Write to the Reconfiguration Interface sections.
  • Updated Using Configuration Files section to with a detailed description of when to use configuration files.
  • Updated the steps in Switching Transmitter PLL, Switching Reference Clocks, and Changing PMA Analog Parameters sections.
2014.10.08 Made the following changes:
  • Minor editorial changes. Corrected typographical errors in Ports and Parameters and Native PHY IP Core Embedded Debug sections.
  • Corrected an error in "Example 6-1: Steps to Merge Transceiver Channels" in Document Channel Merging Requirements section.
2014.08.15 Made the following changes:
  • Updated MegaWizard references to IP Catalog or Parameter Editor.
  • Updated table "Avalon Interface Parameters"
    • Added description for Native PHY Debug Master Endpoint.
    • Added Embedded Debug Parameters.
  • Corrected typos and updated values in table "PMA Analog Feature Offsets".
  • Added a new table "Valid Maximum Pre-Emphasis Settings" in Changing Analog Parameters Section.
  • Updated the description for 0xB reconfiguration address bit[7:5] in table "PRBS Checker Offsets".
  • Updated the Unsupported Features section and removed some unsupported features.
  • Changed the name of Transceiver and PLL Address Map to Arria 10 Transceiver Register Map. Updated the description to better explain the scope of the register map.
  • Added a new section for Embedded Debug feature.
2013.12.02 Initial release.

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