Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

2.6.5.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core

The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core implements the Ethernet protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard. The PHY IP core consists of a physical coding sublayer (PCS) function and an embedded physical media attachment (PMA). You can dynamically switch the PHY operating speed.

Note: Intel FPGAs implement and support the required Media Access Control (MAC) and PHY (PCS+PMA) IP to interf