Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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2.6.5.3.1. Clocking and Reset Sequence

Clocking Requirements:
  • For 64-bit XGMII, the 156.25 MHz clock must have zero ppm difference with reference clock of 10G transceiver PLL. Therefore, the 156.25 MHz clock must derived from the transceiver 10G reference clock for 1G/2.5G/10G (MGBASE-T) variant.
  • For 32-bit XGMII, the 312.5 MHz clock must have zero ppm difference with reference clock of 10G transceiver PLL. Therefore, the 312.5 MHz clock must derived from the transceiver 10G reference clock for 10M/100M/1G/2.5G/5G/10G (USXGMII) variant.

Reset sequence for all configurations is handled by the transceiver reset controller. For 1G/2.5G and 1G/2.5G/10G (MGBASE-T), transceiver reset sequence is automatically triggered after completion of speed switching/reconfiguration in the MAC+PHY example design.

The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core for Intel® Arria® 10 devices supports up to ±100 ppm clock frequency difference for a maximum packet length of 16,000 bytes.

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