Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.4.2. General and Datapath Parameters

You can customize your instance of the Native PHY IP core by specifying parameter values. In the Parameter Editor, the parameters are organized in the following sections for each functional block and feature:
  • General, Common PMA Options, and Datapath Options
  • TX PMA
  • RX PMA
  • Standard PCS
  • Enhanced PCS
  • PCS Direct Datapath
  • Dynamic Reconfiguration
  • Analog PMA Settings (Optional)
  • Generation Options
Table 9.  General, Common PMA Options, and Datapath Options
Parameter Value Description
Message level for rule violations

error

warning

Specifies the messaging level for parameter rule violations. Selecting error causes all rule violations to prevent IP generation. Selecting warning displays all rule violations as warnings in the message window and allows IP generation despite the violations. 22
VCCR_GXB and VCCT_GXB supply voltage for the Transceiver

0_9V, 1_0V, 1_1V

Selects the VCCR_GXB and VCCT_GXB supply voltage for the Transceiver.
Note: This option is only used for GUI rule validation. Use Quartus Prime Setting File (.qsf) assignments to set this parameter in your static design.
Transceiver Link Type

sr, lr

Selects the type of transceiver link. sr-Short Reach (Chip-to-chip communication), lr-Long Reach (Backplane communication).
Note: This option is only used for GUI rule validation. Use Quartus Prime Setting File (.qsf) assignments to set this parameter in your static design.
Transceiver configuration rules

User Selection

Specifies the valid configuration rules for the transceiver.

This parameter specifies the configuration rule against which the Parameter Editor checks your PMA and PCS parameter settings for specific protocols. Depending on the transceiver configuration rule selected, the Parameter Editor validates the parameters and options selected by you and generates error messages or warnings for all invalid settings.

To determine the transceiver configuration rule to be selected for your protocol, refer to the "Transceiver Configuration Rule Parameters" table below for more details about each transceiver configuration rule.

This parameter is used for rule checking and is not a preset. You need to set all parameters for your protocol implementation.

PMA configuration rules

Basic

SATA/SAS

QPI

GPON

Specifies the configuration rule for PMA.

Select Basic for all other protocol modes except for SATA, GPON, and QPI.

SATA (Serial ATA) can be used only if the Transceiver configuration rule is set to Basic/Custom (Standard PCS).

GPON can be used only if the Transceiver configuration rule is set to Basic (Enhanced PCS).

QPI can be used only if the Transceiver configuration rule is set to PCS Direct.

Transceiver mode

TX/RX Duplex

TX Simplex

RX Simplex

Specifies the operational mode of the transceiver.

  • TX/RX Duplex : Specifies a single channel that supports both transmission and reception.
  • TX Simplex : Specifies a single channel that supports only transmission.
  • RX Simplex : Specifies a single channel that supports only reception.

The default is TX/RX Duplex.

Number of data channels 1<n>

Specifies the number of transceiver channels to be implemented. The maximum number of channels available, ( <n> ), depends on the package you select.

The default value is 1.

Data rate < valid Transceiver data rate >

Specifies the data rate in megabits per second (Mbps).

Enable datapath and interface reconfiguration On/Off

When you turn this option on, you can preconfigure and dynamically switch between the Standard PCS, Enhanced PCS, and PCS direct datapaths.

The default value is Off.

Enable simplified data interface On/Off

By default, all 128-bits are ports for the tx_parallel_data and rx_parallel_data buses are exposed. You must understand the mapping of data and control signals within the interface. Refer to the Enhanced PCS TX and RX Control Ports section for details about mapping of data and control signals.

When you turn on this option, the Native PHY IP core presents a simplified data and control interface between the FPGA fabric and transceiver. Only the sub-set of the 128-bits that are active for a particular FPGA fabric width are ports.

The default value is Off.23

Provide separate interface for each channel On/Off

When selected the Native PHY IP core presents separate data, reset and clock interfaces for each channel rather than a wide bus.

Table 10.  Transceiver Configuration Rule Parameters
Transceiver Configuration Setting Description
Basic/Custom (Standard PCS) Enforces a standard set of rules within the Standard PCS. Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules.
Basic/Custom w /Rate Match (Standard PCS) Enforces a standard set of rules including rules for the Rate Match FIFO within the Standard PCS. Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules.
CPRI (Auto) Enforces rules required by the CPRI protocol. The receiver word aligner mode is set to Auto. In Auto mode, the word aligner is set to deterministic latency.
CPRI (Manual) Enforces rules required by the CPRI protocol. The receiver word aligner mode is set to Manual. In Manual mode, logic in the FPGA fabric controls the word aligner.
GbE Enforces rules that the 1 Gbps Ethernet (1 GbE) protocol requires.
GbE 1588 Enforces rules for the 1 GbE protocol with support for Precision time protocol (PTP) as defined in the IEEE 1588 Standard.
Gen1 PIPE Enforces rules for a Gen1 PCIe* ® PIPE interface that you can connect to a soft MAC and Data Link Layer.
Gen2 PIPE Enforces rules for a Gen2 PCIe PIPE interface that you can connect to a soft MAC and Data Link Layer.
Gen3 PIPE Enforces rules for a Gen3 PCIe PIPE interface that you can connect to a soft MAC and Data Link Layer.
Basic (Enhanced PCS) Enforces a standard set of rules within the Enhanced PCS. Select these rules to implement protocols requiring blocks within the Enhanced PCS or protocols not covered by the other configuration rules.
Interlaken Enforces rules required by the Interlaken protocol.
10GBASE-R Enforces rules required by the 10GBASE-R protocol.
10GBASE-R 1588 Enforces rules required by the 10GBASE-R protocol with 1588 enabled.
10GBASE-R w/KR FEC Enforces rules required by the 10GBASE-R protocol with KR FEC block enabled.
40GBASE-R w/KR FEC Enforces rules required by the 40GBASE-R protocol with the KR FEC block enabled.
Basic w/KR FEC Enforces a standard set of rules required by the Enhanced PCS when you enable the KR FEC block. Select this rule to implement custom protocols requiring blocks within the Enhanced PCS or protocols not covered by the other configuration rules.
PCS Direct Enforces rules required by the PCS Direct mode. In this configuration the data flows through the PCS channel, but all the internal PCS blocks are bypassed. If required, the PCS functionality can be implemented in the FPGA fabric.
22 Although you can generate the PHY with warnings, you can not compile the PHY in Quartus Prime.
23 This option cannot be used, if you intend to dynamically reconfigure between PCS datapaths, or reconfigure the interface of the transceiver.

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