Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Public
Document Table of Contents

6.2.1. Reading from the Reconfiguration Interface

Reading from the reconfiguration interface of the Transceiver Native PHY IP core or Transceiver PLL IP core retrieves the current value at a specific address.
Figure 270. Reading from the Reconfiguration Interface
Note: You have to provide at least three reconfig_clk cycles for each read address when you perform back-to-back reads if you keep reconfig_read asserted during the entire read process, or else you have to reassert reconfig_read for each read address.

After the reconfig_read signal is asserted, the reconfig_waitrequest signal asserts for a few reconfig_clock cycles, then deasserts. This deassertion indicates the reconfig_readdata bus contains valid data.

Note: You must check for the internal configuration bus arbitration before performing reconfiguration. Refer to the Arbitration section for more details about requesting access to and returning control of the internal configuration bus from PreSICE.