Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.6.5.5.7. Transceiver Status and Reconfiguration Signals

Table 166.  Control and Status Signals
Signal Name Direction Width Description
rx_is_lockedtodata

Output

1

Asserted when the CDR is locked to the RX data.

tx_cal_busy

Output

1

Asserted when TX calibration is in progress.

rx_cal_busy

Output

1

Asserted when RX calibration is in progress.

Transceiver reconfiguration signals for Arria 10 devices
reconfig_clk Input 1

Reconfiguration signals connected to the reconfiguration block. The reconfig_clk signal provides the timing reference for this interface.

reconfig_reset Input 1
reconfig_address Input 10
reconfig_write Input 1
reconfig_read Input 1
reconfig_writedata Input 32
reconfig_readdata Output 32
reconfig_waitrequest Output 1

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