Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

5.2.1.1. Enhanced PCS TX FIFO

The Enhanced PCS TX FIFO provides an interface between the transmitter channel PCS and the FPGA fabric. The TX FIFO can operate for phase compensation between the channel PCS and FPGA fabric. You can also use the TX FIFO as an elastic buffer to control the input data flow, using tx_enh_data_valid. The TX FIFO also allows channel bonding. The TX FIFO has a width of 73 bits and a depth of 16 words.

You can set the TX FIFO partially full and empty thresholds through the Transceiver and PLL Address Map. Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for more details.

The TX FIFO supports the following operating modes:

  • Phase Compensation mode
  • Register mode
  • Interlaken mode
  • Basic mode

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