Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents Power State Management

Table 184.  Power States Defined in the PCIe* SpecificationTo minimize power consumption, the physical layer device must support the following power states.
Power States Description
P0 Normal operating state during which packet data is transferred on the PCIe link.
P0s, P1, and P2 The PHY-MAC layer directs the physical layer to transition into these low-power states.

The PIPE interface in Arria 10 transceivers provides a pipe_powerdown input port for each transceiver channel configured in a PIPE configuration.

The PCIe specification requires the physical layer device to implement power-saving measures when the P0 power state transitions to the low power states. Arria 10 transceivers do not implement these power-saving measures except for putting the transmitter buffer in electrical idle mode in the lower power states.

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