Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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2.3. Arria® 10 Transceiver Protocols and PHY IP Support

Table 8.   Arria® 10 Transceiver Protocols and PHY IP Support
Protocol Transceiver PHY IP Core PCS Support Transceiver Configuration Rule9 Protocol Preset 10
PCIe* Gen3 x1, x2, x4, x8 Native PHY IP core (PIPE)/Hard IP for PCI Express* 11 Standard and Gen3 Gen3 PIPE

PCIe PIPE Gen3 x1

PCIe PIPE Gen3 x8

PCIe Gen2 x1, x2, x4, x8 Native PHY IP (PIPE) core/Hard IP for PCI Express 11 Standard Gen2 PIPE

PCIe PIPE Gen2 x1

PCIe PIPE Gen2 x8

PCIe Gen1 x1, x2, x4, x8 Native PHY IP (PIPE) core/Hard IP for PCI Express 11 Standard Gen1 PIPE User created
1000BASE-X Gigabit Ethernet Native PHY IP core Standard GbE GIGE - 1.25 Gbps
1000BASE-X Gigabit Ethernet with 1588 Native PHY IP core Standard GbE 1588 GIGE - 1.25 Gbps 1588
10GBASE-R Native PHY IP core Enhanced 10GBASE-R 10GBASE-R Low Latency
10GBASE-R 1588 Native PHY IP core Enhanced 10GBASE-R 1588 10GBASE-R 1588
10GBASE-R with KR FEC Native PHY IP core Enhanced 10GBASE-R w/KR FEC 10GBASE-R w/KR FEC
10GBASE-KR and 1000BASE-X 1G/10GbE and 10GBASE-KR PHY IP12 Standard and Enhanced Not applicable

BackPlane_wo_1588

LineSide (optical)

LineSide(optical)_1588

40GBASE-R Native PHY IP core Enhanced Basic (Enhanced PCS) Low Latency Enhanced PCS 13
40GBASE-R with FEC/40GBASE-KR4 14 Native PHY IP core Enhanced Basic w/KR FEC User created
100GBASE-R via CAUI-4/CPPI-4/BP and CEI-25G Native PHY IP core Enhanced and PCS Direct Basic (Enhanced PCS) / PCS Direct Low Latency GT15
100GBASE-R via CAUI Native PHY IP core Enhanced Basic (Enhanced PCS) Low Latency Enhanced PCS 16
100GBASE-R via CAUI with FEC Native PHY IP core Enhanced Basic w/KR FEC User created
XAUI XAUI PHY IP core Soft PCS Not applicable Not applicable
SPAUI Native PHY IP core Standard and Enhanced

Basic/Custom (Standard PCS)

Basic (Enhanced PCS)

User created
DDR XAUI Native PHY IP core Standard and Enhanced

Basic/Custom (Standard PCS)

Basic (Enhanced PCS)

User created
Interlaken (CEI-6G/11G) 17 Native PHY IP core Enhanced Interlaken

Interlaken 10x12.5Gbps

Interlaken 6x10.3Gbps

Interlaken 1x6.25Gbps

OTU-4 (100G) via OTL4.10/OIF SFI-S Native PHY IP core Enhanced Basic (Enhanced PCS) SFI-S 64:64 4x11.3 Gbps18
OTU-3 (40G) via OTL3.4/OIF SFI-5.2/SFI-5.1 Native PHY IP core Enhanced Basic (Enhanced PCS) User created
OTU-2 (10G) via SFP+/SFF-8431/CEI-11G Native PHY IP core Enhanced Basic (Enhanced PCS) User created
OTU-2 (10G) via OIF SFI-5.1s Native PHY IP core Enhanced Basic (Enhanced PCS) User created
OTU-1 (2.7G) Native PHY IP core Standard Basic/Custom (Standard PCS) User created
SONET/SDH STS-768/STM-256 (40G) via OIF SFI-5.2/STL256.4 Native PHY IP core Enhanced Basic (Enhanced PCS) User created
SONET/SDH STS-768/STM-256 (40G) via OIF SFI-5.1 Native PHY IP core Enhanced Basic (Enhanced PCS) User created
SONET/SDH STS-192/STM-64 (10G) via SFP+/SFF-8431/CEI-11G Native PHY IP core Enhanced Basic (Enhanced PCS) User created
SONET/SDH STS-192/STM-64 (10G) via OIF SFI-5.1s/SxI-5/SFI-4.2 Native PHY IP core Enhanced Basic (Enhanced PCS) User created
SONET STS-96 (5G) via OIF SFI-5.1s Native PHY IP core Enhanced Basic/Custom (Standard PCS) SONET/SDH OC-96
SONET/SDH STS-48/STM-16 (2.5G) via SFP/TFI-5.1 Native PHY IP core Standard Basic/Custom (Standard PCS) SONET/SDH OC-48
SONET/SDH STS-12/STM-4 (0.622G) via SFP/TFI-5.1 Native PHY IP core 19 Standard Basic/Custom (Standard PCS) SONET/SDH OC-12
Intel® QPI 1.1/2.0 Native PHY IP core PCS Direct PCS Direct User created
SD-SDI/HD-SDI/3G-SDI Native PHY IP core Standard Basic/Custom (Standard PCS)

3G/HD SDI NTSC

3G/HD SDI PAL

Vx1 Native PHY IP core Standard Basic/Custom (Standard PCS) User created
DisplayPort 20 Native PHY IP core Standard Basic/Custom (Standard PCS) User created

1.25G/ 2.5G

10G GPON/EPON

Native PHY IP core Enhanced Basic (Enhanced PCS) User created
2.5G/1.25G GPON/EPON Native PHY IP core Standard Basic/Custom (Standard PCS) User created
16G/10G Fibre Channel Native PHY IP core Enhanced Basic (Enhanced PCS) User created
8G/4G/2G/1G Fibre Channel Native PHY IP core Standard Basic/Custom (Standard PCS) User created
EDR Infiniband x1, x4 Native PHY IP core

Enhanced (low latency mode)

PCS Direct

Basic (Enhanced PCS)

PCS Direct

User created
FDR/FDR-10 Infiniband x1, x4, x12 Native PHY IP core Enhanced Basic (Enhanced PCS) User created
SDR/DDR/QDR Infiniband x1, x4, x12 Native PHY IP core Standard Basic/Custom (Standard PCS) User created
CPRI v6.1 12.16512/CPRI v6.0 10.1376 Gbps Native PHY IP core Enhanced

10GBASE-R 1588

10GBASE-R

User created
CPRI 4.2/OBSAI RP3 v4.2 Native PHY IP core Standard CPRI (Auto) / CPRI (Manual)

CPRI 9.8Gbps Auto Mode

CPRI 9.8 Gbps Manual Mode

SRIO 2.2/1.3 Native PHY IP core Standard Basic/Custom with Rate Match(Standard PCS) Serial Rapid IO 1.25 Gbps
SAS 3.0 Native PHY IP core Enhanced Basic (Enhanced PCS) User created
SATA 3.0/2.0/1.0 and SAS 2.0/1.1/1.0 Native PHY IP core Standard Basic/Custom (Standard PCS)

SAS Gen2/Gen1.1/Gen1

SATA Gen3/Gen2/Gen1

HiGig/HiGig+/HiGig2/HiGig2+ Native PHY IP core Standard Basic/Custom (Standard PCS) User created
JESD204A / JESD204B Native PHY IP core Standard and Enhanced Basic/Custom (Standard PCS) Basic (Enhanced PCS) 21 User created
ASI Native PHY IP core Standard Basic/Custom (Standard PCS) User created
SPI-5 (100G) / SPI-5 (50G) Native PHY IP core Enhanced Basic (Enhanced PCS) User created
Custom and other protocols Native PHY IP core

Standard and Enhanced

PCS Direct

Basis/Custom (Standard PCS)

Basic (Enhanced PCS)

Basic/Custom with Rate Match (Standard PCS)

PCS Direct

User created
9 For more information about Transceiver Configuration Rules, refer to Using the Intel® Arria® 10Transceiver Native PHY IP Core section.
10 For more information about Protocol Presets, refer to Using the Intel® Arria® 10Transceiver Native PHY IP Core section.
11 Hard IP for PCI Express is also available as a separate IP core.
12 The 1G/10GbE and 10GBASE-KR PHY IP core includes the necessary soft IP for link training, auto speed negotiation, and sequencer functions.
13 To implement 40GBASE-R using the Low Latency Enhanced PCS preset, change the number of data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.
14 Link training, auto speed negotiation and sequencer functions are not included in the Native PHY IP. The user would have to create soft logic to implement these functions when using Native PHY IP.
15 Low Latency GT protocol preset requires some modification to implement CAUI-4/CPPI-4/BP-4 and CEI-25G.
16 To implement 100GBASE-R via CAUI using the Low Latency Enhanced PCS preset, change the number of data channels to 10 and select appropriate PCS-FPGA Fabric and PCS-PMA width.
17 A Transmit PCS soft bonding logic required for multi-lane bonding configuration is provided in the design example.
18 To implement OTU-4 (100G) via OTL4.10/OIF SFI-S using SFI-S 64:64 4x11.3Gbps preset, change the number of data channels to 10 for OTL4.10 or user desired number of channels and datarate implemented for SFI-S.
19 The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. For receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.
20 To meet DisplayPort TX electrical full compliance to VESA DisplayPort Standard version 1.3 and VESA DisplayPort PHY Compliance Specification version 1.2b , VCCT_GXB & VCCR_GXB needs to be 1.03V or higher. Test Refer to AN745: Design Guidelines for DisplayPort and HDMI Interfaces for further details.
21 For JESD204B, Enhanced PCS is used when the data rate is above 12.0 Gbps

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