Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Public
Document Table of Contents

2.3. Arria® 10 Transceiver Protocols and PHY IP Support

Table 8.   Arria® 10 Transceiver Protocols and PHY IP Support
Protocol Transceiver PHY IP Core PCS Support Transceiver Configuration Rule9 Protocol Preset 10
PCIe* Gen3 x1, x2, x4, x8 Native PHY IP core (PIPE)/Hard IP for PCI Express* 11 Standard and Gen3 Gen3 PIPE

PCIe PIPE Gen3 x1

PCIe PIPE Gen3 x8

PCIe Gen2 x1, x2, x4, x8 Native PHY IP (PIPE) core/Hard IP for PCI Express 11 Standard Gen2 PIPE

PCIe PIPE Gen2 x1

PCIe PIPE Gen2 x8

PCIe Gen1 x1, x2, x4, x8