Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

7.2.6. Rate Switch Flag Register

The rate switch flag is for CDR charge pump calibration. Each SOF has CDR default charge pump settings. After power up, these settings are loaded into the PreSICE memory space. If you change the line rate, it may require new charge pump settings, which are stored into the Avalon® memory-mapped interface reconfiguration register space. During RX PMA calibration (including CDR), PreSICE needs to know which set of CDR charge pump setting to use.

If you set 0x166[7] = 0x1, PreSICE assumes the setting in its memory space is still valid. If after a rate change you set 0x166[7]=0x0, PreSICE uses the setting from the Avalon® memory-mapped interface reconfiguration register uploaded from the dynamic reconfiguration interface or MIF streamed in. After calibration, 0x166[7] = 0x1 is set automatically and PreSICE uses the settings in its memory space. The rate switch flag only tells PreSICE where to obtain the CDR charge pump settings for CDR calibration. The rate switch flag should be used only when there is a rate change.

Multiple MIF files are required for rate change and reconfiguration. When the MIF, which you want to stream in, has CDR charge pump setting 0x139[7] and 0x133[7:5] that is different from the previous MIF, you need to recalibrate with 0x166[7]=0x0. If you stream in the whole MIF, the 0x166[7] is set to the correct value inside the MIF. If you stream in reduced MIF, you need to check if CDR charge pump setting 0x139[7] and 0x133[7:5] are inside the reduced MIF or not. If the reduced MIF has CDR charge pump setting 0x139[7] and 0x133[7:5] updated, you need to set 0x166[7]=0x0, if the reduced MIF does not include 0x139[7] and 0x133[7:5], you need to set 0x166[7]=0x1.

Table 303.  Rate Switch Flag Register for CDR Calibration
Bit Description
0x166[7]

Rate switch flag register. Power up default value is 0x1.

0x1, PreSICE uses the default CDR charge pump bandwidth from the default memory space.

0x0, PreSICE uses the CDR charge pump bandwidth setting from the DPRIO register space.

If you use the Avalon® memory-mapped interface reconfiguration to perform a rate change, you must write 0x0 to 0x166[7] before returning the bus to PreSICE.

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