Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.6.6. XAUI PHY IP Core

In a XAUI configuration, the transceiver channel data path is configured using a soft PCS. The XAUI configuration provides the transceiver channel datapath, clocking, and channel placement guidelines. You can implement a XAUI link using the IP Catalog. Under Ethernet in the Interfaces menu, select the XAUI PHY IP core. The XAUI PHY IP core implements the XAUI PCS in soft logic.

XAUI is a specific physical layer implementation of the 10 Gigabit Ethernet link defined in the IEEE 802.3ae-2008 specification. The XAUI PHY uses the XGMII interface to connect to the IEEE802.3 MAC and Reconciliation Sublayer (RS). The IEEE 802.3ae-2008 specification requires the XAUI PHY link to support:

  • A 10 Gbps data rate at the XGMII interface
  • Four lanes each at 3.125 Gbps at the PMD interface
Figure 83. XAUI and XGMII Layers


Intel® 's XAUI PHY IP core implements the IEEE 802.3 Clause 48 specification to extend the operational distance of the XGMII interface and reduce the number of interface signals.

XAUI extends the physical separation possible between the 10 Gbps Ethernet MAC function and the Ethernet standard PHY component to one meter. The XAUI PHY IP core accepts 72-bit data (single data rate–SDR XGMII) from the application layer at 156.25 Mbps. The serial interface runs at 4 × 3.125 Gbps.

Figure 84. XAUI PHY IP Core

Intel® 's third-party IP partner for Dual Data Rate XAUI (DDR XAUI or DXAUI) and Reduced XAUI (RXAUI) support is MorethanIP (MTIP).

XAUI does not support open compute project (OCP) networking.

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