Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents XAUI PHY Clocks, Reset, and Powerdown Interfaces

Figure 91. Clock Inputs and Outputs for IP Core with Soft PCS
Table 176.   Clock and Reset Signals
Signal Name Direction Description
pll_ref_clk Input This is a 156.25 MHz reference clock that is used by the CDR logic.

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