Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents CMU PLL IP Core

Table 240.  CMU PLL Parameters and Settings
Parameters Range Description

Message level for rule violations



Specifies the messaging level to use for parameter rule violations.
  • Error - Causes all rule violations to prevent IP generation.
  • Warning - Displays all rule violations as warnings and allows IP generation in spite of violations.





Specifies the VCO bandwidth.

Higher bandwidth reduces PLL lock time, at the expense of decreased jitter rejection.

Number of PLL reference clocks

1 to 5

Specifies the number of input reference clocks for the CMU PLL.

You can use this parameter for data rate reconfiguration.

Selected reference clock source

0 to 4

Specifies the initially selected reference clock input to the CMU PLL.

TX PLL Protocol mode