Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

3.1.4.2. CMU PLL IP Core

Table 240.  CMU PLL Parameters and Settings
Parameters Range Description

Message level for rule violations

Error

Warning

Specifies the messaging level to use for parameter rule violations.
  • Error - Causes all rule violations to prevent IP generation.
  • Warning - Displays all rule violations as warnings and allows IP generation in spite of violations.

Bandwidth

Low

Medium

High

Specifies the VCO bandwidth.

Higher bandwidth reduces PLL lock time, at the expense of decreased jitter rejection.

Number of PLL reference clocks

1 to 5

Specifies the number of input reference clocks for the CMU PLL.

You can use this parameter for data rate reconfiguration.

Selected reference clock source

0 to 4

Specifies the initially selected reference clock input to the CMU PLL.

TX PLL Protocol mode

BASIC

PCIe*

This parameter governs the rules for correct protocol specific settings. Certain features of the PLL are only available for specific protocol configuration rules. This parameter is not a preset .

You must set all the other parameters for your protocol.

PLL reference clock frequency

Refer to the GUI

Selects the input reference clock frequency for the PLL.

PLL output frequency

Refer to the GUI

Specify the target output frequency for the PLL.

Multiply factor (M-Counter)

Read only

Displays the M-multiplier value.

Divide factor (N-Counter)

Read only

 

Displays the N-counter value.

Divide factor (L-Counter)

Read only

Displays the L-counter value.

Table 241.  CMU PLL—Dynamic Reconfiguration
Parameters Range Description

Enable dynamic reconfiguration

On/Off

Enables the PLL reconfiguration interface. Enables the simulation models and adds more ports for reconfiguration.

Enable Native PHY Debug Master Endpoint

On/Off

When you turn this option On, the transceiver PLL IP core includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally to the Avalon® memory-mapped interface slave interface for dynamic reconfiguration. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for more details.

Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE

On/Off

When enabled, the reconfig_waitrequest does not indicate the status of Avalon® memory-mapped interface arbitration with PreSICE. The Avalon® memory-mapped interface arbitration status is reflected in a soft status register bit. (Only available if "Enable control and status registers feature" is enabled).

Enable capability registers

On/Off

Enables capability registers that provide high- level information about the CMU PLL's configuration.

Set user-defined IP identifier

 

Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled.

Enable control and status registers

On/Off

Enables soft registers for reading status signals and writing control signals on the PLL interface through the embedded debug logic.

Configuration file prefix

 

Enter the prefix name for the configuration files to be generated.

Generate SystemVerilog package file 

On/Off

Generates a SystemVerilog package file containing all relevant parameters used by the PLL.

Generate C header file

On/Off

Generates a C header file containing all relevant parameters used by the PLL.

Generate MIF (Memory Initialize File)  

On/Off

Generates a MIF file that contains the current configuration.

Use this option for reconfiguration purposes in order to switch between different PLL configurations.

Table 242.  CMU PLL—Generation Options
Parameters Range Description

Generate parameter documentation file

On/Off

 Generates a .csv file which contains the descriptions of all CMU PLL parameters and values.

Table 243.  CMU PLL IP Ports
Port Range Clock Domain Description

pll_powerdown

input

Asynchronous

Resets the PLL when asserted high.

pll_refclk0

input

N/A

Reference clock input port 0.

There are 5 reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter.

pll_refclk1

input

N/A

Reference clock input port 1.

pll_refclk2

input

N/A

Reference clock input port 2.

pll_refclk3

input

N/A

Reference clock input port 3.

pll_refclk4

input

N/A

Reference clock input port 4.

tx_serial_clk

output

N/A

High speed serial clock output port for GX channels. Represents the x1 clock network.

pll_locked

output

Asynchronous

Active high status signal which indicates if PLL is locked.

reconfig_clk0

input

N/A

Optional Avalon® interface clock. Used for PLL reconfiguration. The reconfiguration ports appear only if the Enable Reconfiguration parameter is selected in the PLL IP Core GUI. When this parameter is not selected, the ports are set to OFF internally.

reconfig_reset0

input

reconfig_clk0

Used to reset the Avalon® interface. Asynchronous to assertion and synchronous to deassertion.

reconfig_write0

input

reconfig_clk0

Active high write enable signal.

reconfig_read0

input

reconfig_clk0

Active high read enable signal.

reconfig_address0[9:0]

input

reconfig_clk0

10-bit address bus used to specify address to be accessed for both read and write operations.

reconfig_writedata0[31:0]

input

reconfig_clk0

32-bit data bus. Carries the write data to the specified address.

reconfig_readdata0[31:0]

output

reconfig_clk0

32-bit data bus. Carries the read data from the specified address.

reconfig_waitrequest0

output

reconfig_clk0

Indicates when the Avalon® interface signal is busy. When asserted, all inputs must be held constant.

pll_cal_busy

output

Asynchronous

Status signal that is asserted high when PLL calibration is in progress.

Perform logical OR with this signal and the tx_cal_busy port on the reset controller IP.

Did you find the information on this page useful?

Characters remaining:

Feedback Message