Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

6.4. Multiple Reconfiguration Profiles

You can optionally enable multiple configurations or profiles in the same Native PHY IP or ATX PLL IP core Parameter Editor (or both) for performing dynamic reconfiguration. This allows the IP Parameter Editor to create, store, and analyze the parameter settings for multiple configurations or profiles.

When you enable the multiple reconfiguration profiles feature, the Native PHY IP Core, ATX PLL IP core, or both can generate configuration files for all the profiles in the format desired (SystemVerilog package, MIF, or C header file). The configuration files are located in the <IP instance name>\altera_xcvr_<IP type>_a10_<quartus version>\synth\reconfig subfolder of the IP instance with the configuration profile index added to the filename. For example, the configuration file for Profile 0 is stored as <filename_CFG0.sv>. The Quartus® Prime Timing Analyzer Timing Analyzer includes the necessary timing paths for all the configurations based on initial and target profiles. You can also generate reduced configuration files that contain only the attributes that differ between the multiple configured profiles. You can create up to eight reconfiguration profiles (Profile 0 to Profile 7) at a time for each instance of the Native PHY/ATX PLL IP core.

You can optionally allow the Native PHY IP core to include PMA Analog settings in the configuration files by enabling the feature