Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.7.2.1.1. Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps)

In a PIPE configuration, Native PHY IP Core provides an input signal pipe_rate [1:0] that is functionally equivalent to the RATE signal specified in the PCIe* specification. A change in value from 2'b00 to 2'b01 on this input signal pipe_rate [1:0] initiates a data rate switch from Gen1 to Gen2. A change in value from 2'b01 to 2'b00 on the input signal initiates a data rate switch from Gen2 to Gen1.

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