Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.4.5.1. General Options

The General Options allow you to specify options common to 10GBASE-KR mode.
Table 129.  General Options Parameters
Parameter Name Options Description
Enable internal PCS reconfiguration logic On

Off

This parameter is only an option when SYNTH_SEQ = 0. When set to 0, it does not include the reconfiguration module or expose the start_pcs_reconfig or rc_busy ports. When set to 1, it provides a simple interface to initiate reconfiguration between 1G and 10G modes.
Enable IEEE 1588 Precision Time Protocol On

Off

When you turn on this parameter, you enable the IEEE 1588 Precision Time Protocol logic for both 1G and 10G modes.
Enable M20K block ECC protection On

Off

When you turn on this parameter, you enable error correction code (ECC) support on the embedded Nios CPU system. This parameter is only valid for the backplane variant.
Enable tx_pma_clkout port On

Off

When you turn on this parameter, the tx_pma_clkout port is enabled. Refer to the Clock and Reset Interfaces section for more information about this port.
Enable rx_pma_clkout port On

Off

When you turn on this parameter, the rx_pma_clkout port is enabled. Refer to the Clock and Reset Interfaces section for more information about this port.
Enable tx_divclk port On

Off

When you turn on this parameter, the tx_divclk port is enabled. Refer to the Clock and Reset Interfaces section for more information about this port.
Enable rx_divclk port On

Off

When you turn on this parameter, the rx_divclk port is enabled. Refer to the Clock and Reset Interfaces section for more information about this port.
Enable tx_clkout port On

Off

When you turn on this parameter, the tx_clkout port is enabled. Refer to the Clock and Reset Interfaces section for more information about this port.
Enable rx_clkout port On

Off

When you turn on this parameter, the rx_clkout port is enabled. Refer to the Clock and Reset Interfaces section for more information about this port.
Enable Hard PRBS support and Native PHY Debug Master Endpoint support On

Off

When you turn on this parameter, you enable the Native PHY Debug Master Endpoint (NPDME) and Hard PRBS data generation and checking logic in the Native PHY. The transceiver toolkit (TTK) requires NPDME to be enabled in the Native PHY IP core.
Reference clock frequency 644.53125 MHz

322.265625 MHz

Specifies the input reference clock frequency. The default is 322.265625 MHz.
Enable additional control and status ports On

Off

When you turn this option on, the core includes the rx_block_lock and rx_hi_ber output.
Include FEC sublayer On

Off

When you turn on this parameter, the core includes logic to implement FEC and a soft 10GBASE-R PCS. This is applicable only for the 10G mode.
Set FEC_ability bit on power up and reset On

Off

When you turn on this parameter, the core sets the Assert KR FEC Ability bit (0xB0[16]) FEC ability bit during power up and reset, causing the core to assert the FEC ability. This option is required for FEC functionality.
Set FEC_Enable bit on power up and reset On

Off

When you turn on this parameter, the core sets the KR FEC Request bit (0xB0[18]) during power up and reset, causing the core to request the FEC ability during Auto Negotiation. This option is required for FEC functionality.

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