184.108.40.206. Implementing PLL Feedback Compensation Bonding Mode
The data rate is limited by the x6 network speed limit. A disadvantage of using PLL feedback compensation bonding is that it consumes more PLL resources. Each transceiver bank consumes one PLL and one master CGB.
In PLL feedback compensation bonding mode, the N counter (reference clock divider) is bypassed in order to ensure that the reference clock skew is minimized between the PLLs in the bonded group. Because the N counter is bypassed, the PLL reference clock has a fixed value for any given data rate.
The PLL IP Core Parameter Editor window displays the required data rate in the PLL reference clock frequency drop down menu.
Steps to implement a PLL Feedback Compensation B