Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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3.11.2.2. Implementing PLL Feedback Compensation Bonding Mode

In this bonding mode, the channel span limitations of xN bonding mode are removed. This is achieved by dividing all channels into multiple bonding groups.
Figure 198. PHY IP Core and PLL IP Core Connection for PLL Feedback Compensation Bonding


The data rate is limited by the x6 network speed limit. A disadvantage of using PLL feedback compensation bonding is that it consumes more PLL resources. Each transceiver bank consumes one PLL and one master CGB.

In PLL feedback compensation bonding mode, the N counter (reference clock divider) is bypassed in order to ensure that the reference clock skew is minimized between the PLLs in the bonded group. Because the N counter is bypassed, the PLL reference clock has a fixed value for any given data rate.

The PLL IP Core Parameter Editor window displays the required data rate in the PLL reference clock frequency drop down menu.

Steps to implement a PLL Feedback Compensation Bonding Configuration

  1. Instantiate the PLL IP core (ATX PLL or fPLL) you want to use in your design. Refer to Instantiating the ATX PLL IP Core or Instantiating the fPLL IP Core for detailed steps. Because the CMU PLL cannot drive the master CGB, only the ATX PLL or fPLL can be used for feedback compensation bonding.
  2. Configure the PLL IP core using the IP Parameter Editor.
    • If you use the ATX PLL, set the following configuration settings:
      • Under the Master Clock Generation Block Tab
        • Enable Include Master Clock Generation Block.
        • Turn ON Enable Bonding Clock output ports.
        • Turn ON Enable feedback compensation bonding.
      • Under the Dynamic Reconfiguration Tab
        • Turn ON Enable dynamic reconfiguration
    • If you use the fPLL, set the following configuration settings:
      • Under the PLL Tab
        • Set the PLL Feedback type to feedback compensation bonding.
      • Under the Master Clock Generation Block Tab
        • Turn ON Enable Bonding Clock output ports.
      • Under the Dynamic Reconfiguration Tab
        • Turn ON Enable dynamic reconfiguration
  3. Configure the Native PHY IP core using the IP Parameter Editor
    • Set the Native PHY IP core TX Channel bonding mode to either PMA bonding or PMA/PCS bonding.
    • Turn ON Enable dynamic reconfiguration
  4. Create a top level wrapper to connect the PLL IP cores to Native PHY IP core.
    • In this case, the PLL IP core has tx_bonding_clocks output bus with width [5:0].
    • The Native PHY IP core has tx_bonding_clocks input bus with width [5:0] multiplied by the number of channels in a transceiver bank. (six channels in the transceiver bank).
    • Unlike the x6/xN bonding mode, for this mode, the PLL should be instantiated multiple times. (One PLL is required for each transceiver bank that is a part of the bonded group.) Instantiate a PLL for each transceiver bank used.
    • Connect the tx_bonding_clocks output from each PLL to (up to) six channels in the same transceiver bank.
    • Connect the PLL IP core to the PHY IP core by duplicating the output of the PLL[5:0] for the number of transceiver channels used in the bonding group.

Steps to recalibrate the PLL after power up calibration

  1. Dynamic reconfigure the PLL to change the feedback from the master CGB to feedback from PLL.
    • For ATX PLL, Read-Modify-Write 0x1 to offset address 0x110[2] of the ATX PLL.
    • For fPLL, Read-Modify-Write 0x1 to offset address 0x126[0] of the fPLL.
  2. Recalibrate the PLL.
  3. After recalibration completes, ensure the PLL achieves lock. Dynamic reconfigure the PLL to change the feedback to master CGB.
    • For ATX PLL, Read-Modify-Write 0x0 to offset address 0x110[2] of the ATX PLL.
    • For fPLL, Read-Modify-Write 0x0 to offset address 0x126[0] of the fPLL.
  4. Recalibrate TX PMA of all the bonded channels driven by the ATX PLL or the fPLL.
Note: For this 10-channel example, two ATX PLLs are instantiated. Six channels of the tx_bonding_clocks on the Native PHY IP core are connected to the first ATX PLL and the remaining four channels are connected to the second ATX PLL's tx_bonding_clock outputs.

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