Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Public
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2.2.6. Generate the PLL IP Core

After configuring the PLL IP core, complete the following steps to generate the PLL IP core.

  1. Click the Generate HDL button in the Parameter Editor window. The Generation dialog box opens.
  2. In Synthesis options, under Create HDL design for synthesis select Verilog or VHDL.
  3. Select appropriate Simulation options depending on the choice of the hardware description language you selected under Synthesis options.
  4. In Output Directory, select Clear output directories for sel