220.127.116.11.5. Gen3 Power State Management
The PCIe* base specification defines low power states for PHY layer devices to minimize power consumption. The Gen3 PCS does not implement these power saving measures, except when placing the transmitter driver in electrical idle in the low power state. In the P2 low power state, the transceivers do not disable the PIPE block clock.
Did you find the information on this page useful?