Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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4.4.2. Transceiver PHY Reset Controller Parameters

The Quartus Prime software provides a GUI to define and instantiate a Transceiver PHY Reset Controller to reset transceiver PHY and external PLL.
Table 247.  General Options
Name Range Description
Number of transceiver channels 1-1000 Specifies the number of channels that connect to the Transceiver PHY Reset Controller IP core. The upper limit of the range is determined by your FPGA architecture.
Number of TX PLLs 1-1000 Specifies the number of TX PLLs that connect to the Transceiver PHY Reset Controller IP core.
Input clock frequency 1-500 MHz Input clock to the Transceiver PHY Reset Controller IP core. The frequency of the input clock in MHz. The upper limit on the input clock frequency is the frequency achieved in timing closure.
Synchronize reset input On /Off When On, the Transceiver PHY Reset Controller synchronizes the reset to the Transceiver PHY Reset Controller input clock before driving it to the internal reset logic. When Off, the reset input is not synchronized.
Use fast reset for simulation On /Off When On, the Transceiver PHY Reset Controller uses reduced reset counters for simulation.
Separate interface per channel/PLL On /Off When On, the Transceiver PHY Reset Controller provides a separate reset interface for each channel and PLL.
TX PLL
Enable TX PLL reset control On /Off When On, the Transceiver PHY Reset Controller IP core enables the reset control of the TX PLL. When Off, the TX PLL reset control is disabled.
pll_powerdown duration 1-999999999 Specifies the duration of the PLL powerdown period in ns. The value is rounded up to the nearest clock cycle. The default value is 1000 ns.
Synchronize reset input for PLL powerdown On /Off When On, the Transceiver PHY Reset Controller synchronizes the PLL powerdown reset with the Transceiver PHY Reset Controller input clock. When Off, the PLL powerdown reset is not synchronized.
TX Channel
Enable TX channel reset control On /Off When On, the Transceiver PHY Reset Controller enables the control logic and associated status signals for TX reset. When Off, disables TX reset control and status signals.
Use separate TX reset per channel On /Off When On, each TX channel has a separate reset. When Off, the Transceiver PHY Reset Controller uses a shared TX reset controller for all channels.
TX digital reset mode Auto, Manual, Expose Port Specifies the Transceiver PHY Reset Controller behavior when the pll_locked signal is deasserted. The following modes are available:
  • Auto—The associated tx_digitalreset controller automatically resets whenever the pll_locked signal is deasserted. Intel recommends this mode.
  • Manual—The associated tx_digitalreset controller is not reset when the pll_locked signal is deasserted, allowing you to choose corrective action.
  • Expose Port—The tx_manual signal is a top-level signal of the IP core. You can dynamically change this port to Auto or Manual. (1= Manual , 0 = Auto)
tx_analogreset duration 1-999999999

Specifies the time in ns to continue to assert tx_analoglreset after the reset input and all other gating conditions are removed. The value is rounded up to the nearest clock cycle.

Note: Model 1 requires this to be set to 70 µs. Select the Arria 10 Default Settings preset.
tx_digitalreset duration 1-999999999 Specifies the time in ns to continue to assert the tx_digitalreset after the reset input and all other gating conditions are removed. The value is rounded up to the nearest clock cycle.
Note: Model 1 requires this to be set to 70 µs. Select the <Device> Default Settings preset. The default value for Model 2 is 20 ns.
pll_locked input hysteresis 0-999999999 Specifies the amount of hysteresis in ns to add to the pll_locked status input to filter spurious unreliable assertions of the pll_locked signal. A value of 0 adds no hysteresis. A higher value filters glitches on the pll_locked signal. Intel recommends that the amount of hysteresis be longer than treq = 70 μs.
RX Channel
Enable RX channel reset control On /Off When enabled, the IP enables control logic and status signals for the RX reset signals.
Use separate RX reset per channel On /Off When On, each RX channel has a separate reset input. When Off, uses a shared RX reset controller for all channels.
RX digital reset mode Auto, Manual, Expose Port Specifies the Transceiver PHY Reset Controller behavior when the PLL lock signal is deasserted. The following modes are available:
  • Auto—The associated rx_digitalreset controller automatically resets whenever the rx_is_lockedtodata signal is deasserted.
  • Manual—The associated rx_digitalreset controller is not reset when the rx_is_lockedtodata signal is deasserted, allowing you to choose corrective action.
  • Expose Port—The rx_manual signal is a top-level signal of the IP core. If the core includes separate reset control for each RX channel, each RX channel uses its respective rx_is_lockedtodata signal for automatic reset control; otherwise, the inputs are ANDed to provide internal status for the shared reset controller.
rx_analogreset duration 1-999999999 Specifies the time in ns to continue to assert the rx_analogreset after the reset input and all other gating conditions are removed. The value is rounded up to the nearest clock cycle. The default value is 40 ns.
Note: Model 1 requires this to be set to 70 µs. Select the <Device> Default Settings preset.
rx_digitalreset duration 1-999999999 Specifies the time in ns to continue to assert the rx_digitalreset after the reset input and all other gating conditions are removed. The value is rounded up to the nearest clock cycle. The default value is 4000 ns.

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