Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Public
Document Table of Contents

4.4.2. Transceiver PHY Reset Controller Parameters

The Intel® Quartus® Prime software provides a GUI to define and instantiate a Transceiver PHY Reset Controller to reset transceiver PHY and external PLL.
Table 247.  General Options
Name Range Description
Number of transceiver channels 1-1000 Specifies the number of channels that connect to the Transceiver PHY Reset Controller IP core. The upper limit of the range is determined by your FPGA architecture.
Number of TX PLLs 1-1000 Specifies the number of TX PLLs that connect to the Transceiver PHY Reset Controller IP core.
Input clock frequency 1-500 MHz Input clock to the Transceiver PHY Reset Controller IP core. The frequency of the input clock in MHz. The upper limit on the input clock frequency is the frequency achieved in timing closure.
Synchronize reset input On /