Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.7.2.1.7. Gen1 and Gen2 Clock Compensation

PIPE 0 ppm

In compliance with the PIPE specification, Arria 10 receiver channels have a rate match FIFO to compensate for small clock frequency differences up to ±300 ppm between the upstream transmitter and the local receiver clocks.

Consider the following guidelines for PIPE clock compensation:

  • Insert or delete one SKP symbol in an SKP ordered set.
  • Minimum limit is imposed on the number of SKP symbols in SKP ordered set after deletion. An ordered set may have an empty COM case after deletion.
  • Maximum limit is imposed on the number of the SKP symbols in the SKP ordered set after insertion. An ordered set may have more than five symbols after insertion.
  • For INSERT/DELETE cases: The flag status appears on the COM symbol of the SKP ordered set where insertion or deletion occurs.
  • For FULL/EMPTY cases: The flag status appears where the character is inserted or deleted.
    Note: When the PIPE interface is on, it translates the value of the flag to the appropriate pipe_rx_status signal.
  • The PIPE mode also has a “0 ppm” configuration option that you can use in synchronous systems. The Rate Match FIFO Block is not expected to do any clock compensation in this configuration, but latency is minimized.
Figure 94. Rate Match DeletionThis figure shows an example of rate match deletion in the case where two /K28.0/ SKP symbols must be deleted. Only one /K28.0/ SKP symbol is deleted per SKP ordered set received.


Figure 95. Rate Match Insertion The figure below shows an example of rate match insertion in the case where two SKP symbols must be inserted. Only one /K28.0/ SKP symbol is inserted per SKP ordered set received.
Figure 96. Rate Match FIFO FullThe rate match FIFO in PIPE mode automatically deletes the data byte that causes the FIFO to go full and drives pipe_rx_status[2:0] = 3'b101 synchronous to the subsequent data byte. The figure below shows the rate match FIFO full condition in PIPE mode. The rate match FIFO becomes full after receiving data byte D4.


Figure 97. Rate Match FIFO EmptyThe rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that causes the FIFO to become empty and drives pipe_rx_status[2:0] = 3'b110 synchronous to the inserted /K30.7/ (9'h1FE). The figure below shows rate match FIFO empty condition in PIPE mode. The rate match FIFO becomes empty after reading out data byte D3.


The PIPE mode also has a "0 ppm" configuration option that can be used in synchronous systems. The Rate Match FIFO Block is not expected to do any clock compensation in this configuration, but latency is minimized.

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