Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Document Table of Contents 10GBASE-R Bit-Error Rate (BER) Checker

The 10GBASE-R BER checker block is designed in accordance with the 10GBASE-R protocol specification as described in IEEE 802.3-2008 clause-49. After block lock synchronization is achieved, the BER checker starts to count the number of invalid synchronization headers within a 125-μs period. If more than 16 invalid synchronization headers are observed in a 125-μs period, the BER checker provides the status signal rx_enh_highber to the FPGA fabric, indicating a high bit error rate condition.

When the optional control input rx_enh_highber_clr_cnt is asserted, the internal counter for the number of times the BER sta