Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.8.5. Native PHY IP Parameter Settings for CPRI

Table 205.  General and Datapath OptionsThe first two sections of the Parameter Editor for the Native PHY IP provide a list of general and datapath options to customize the transceiver.
Parameter Value
Message level for rule violations

error

warning

Transceiver configuration rules

CPRI (Auto)

CPRI (Manual)

PMA configuration rules

basic

Transceiver mode

TX/RX Duplex

Number of data channels 1-36
Data rate

1228.8 Mbps

2457.6 Mbps

3072 Mbps

4915.2 Mbps

6144 Mbps

8110.08 Mbps

9830.4 Mbps

10137.6 Mbps 47

12165.12 Mbps 47

Enable datapath and interface reconfiguration Off
Enable simplified data interface On
Table 206.  TX PMA Parameters
Parameter Value
TX channel bonding mode

Not Bonded / PMA Bonding Only / PMA and PCS Bonding

TX local clock division factor 1
Number of TX PLL clock inputs per channel 1
Initial TX PLL clock input selection 0
Enable tx_pma_clkout port Off
Enable tx_pma_div_clkout port On
tx_pma_div_clkout division factor 2
Enable tx_pma_elecidle port Off
Enable tx_pma_qpipullup port (QPI) Off
Enable tx_pma_qpipulldn port (QPI) Off
Enable tx_pma_txdetectrx port (QPI) Off
Enable tx_pma_rxfound port (QPI) Off
Enable rx_seriallpbken port Off
Table 207.  RX PMA Parameters
Parameter Value
Number of CDR reference clocks 1
Selected CDR reference clock 0
Selected CDR reference clock frequency Select legal range defined by the Quartus Prime software
PPM detector threshold 1000
CTLE adaptation mode manual
DFE adaptation mode disabled
Number of fixed dfe taps 3
Enable rx_pma_clkout port Off
Enable rx_pma_div_clkout port On
rx_pma_div_clkout division factor 2
Enable rx_pma_clkslip port Off
Enable rx_pma_qpipulldn port (QPI) Off
Enable rx_is_lockedtodata port On
Enable rx_is_lockedtoref port On
Enable rx_set_locktodata and rx_set_locktoref ports Off
Enable rx_seriallpbken port Off
Enable PRBS verifier control and status ports Off
Table 208.  Standard PCS Parameters
Parameters Value
Standard PCS / PMA interface width 20
FPGA fabric / Standard TX PCS interface width 32
FPGA fabric / Standard RX PCS interface width 32
Enable 'Standard PCS' low latency mode Off
TX FIFO mode register_fifo
RX FIFO mode register_fifo
Enable tx_std_pcfifo_full port Off
Enable tx_std_pcfifo_empty port Off
Enable rx_std_pcfifo_full port Off
Enable rx_std_pcfifo_empty port Off
TX byte serializer mode

Serialize x2

RX byte deserializer mode

Deserialize x2

Enable TX 8B/10B encoder On
Enable TX 8B/10B disparity control Off
Enable RX 8B/10B decoder On
RX rate match FIFO mode Disabled
RX rate match insert / delete -ve pattern (hex) 0x00000000
RX rate match insert / delete +ve pattern (hex) 0x00000000
Enable rx_std_rmfifo_full port Off
Enable rx_std_rmfifo_empty port Off
PCI Express* Gen3 rate match FIFO mode Bypass
Enable TX bit slip

Off (CPRI Auto configuration)

On (CPRI Manual configuration)

Enable tx_std_bitslipboundarysel port

Off (CPRI Auto configuration)

On (CPRI Manual configuration)

RX word aligner mode

deterministic latency (CPRI Auto configuration)

manual (FPGA fabric controlled) (CPRI Manual configuration)

RX word aligner pattern length 10
RX word aligner pattern (hex) 0x000000000000017c
Number of word alignment patterns to achieve sync 3 48
Number of invalid data words to lose sync 3 48
Number of valid data words to decrement error count 3 48
Enable fast sync status reporting for deterministic latency SM On / Off
Enable rx_std_wa_patternalign port

On / Off

Enable rx_std_wa_a1a2size port Off
Enable rx_std_bitslipboundarysel port

Off (CPRI Auto configuration)

On (CPRI Manual configuration)

Enable rx_bitslip port

Off (CPRI Auto configuration)

On (CPRI Manual configuration)

All options under Bit Reversal and Polarity Inversion Off
All options under PCIe* Ports Off
Table 209.  Dynamic Reconfiguration
Parameter Value
Enable dynamic reconfiguration Off
Share reconfiguration interface Off
Enable Native PHY Debug Master Endpoint Off
Enable embedded debug Off
Enable capability registers Off
Set user-defined IP identifier 0
Enable control and status registers Off
Enable prbs soft accumulators Off
Configuration file prefix altera_xcvr_native_a10
Generate SystemVerilog package file Off
Generate C header file Off
Generate MIF (Memory Initialization File) Off
Table 210.  Generation Options
Parameter Value
Generate parameter documentation file On
47 10137.6 Mbps and 12165.12 Mbps are implemented by selecting 10GBase-R or 10GBase-R 1588 under Transceiver configuration rules. The Enhanced PCS is selected when the CPRI data rate is 10137.6 Mbps and above.
48 These are unused when the transceiver PHY is in CPRI mode.

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