Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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3.10. PLL Feedback and Cascading Clock Network

The PLL feedback and cascading clock network spans the entire side of the device, and is used for PLL feedback compensation bonding and PLL cascading.

Figure 188. PLL Feedback and Cascading Clock Network


To support PLL feedback compensation bonding and PLL cascading, the following connections are present:

  1. The C counter output of the fPLL drives the feedback and cascading clock network.
  2. The feedback and cascading clock network drives the feedback clock input of all PLLs.
  3. The feedback and cascading clock network drives the reference clock input of all PLLs.
  4. The master CGB’s parallel clock output drives the feedback and cascading clock network.

For PLL cascading, connections (1) and (3) are used to connect the output of one PLL to the reference clock input of another PLL.

The transceivers in Arria 10 devices support fPLL to fPLL, and ATX PLL to fPLL (via dedicated ATX PLL to fPLL cascade path) cascading. Only maximum two PLLs allowed in the cascading chain.
Note: When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for more information.

For PLL feedback compensation bonding, connections (2) and (4) are used to connect the master CGB's parallel clock output to the PLL feedback clock input port.

PLL feedback compensation bonding can be used instead of xN bonding. The primary difference between PLL feedback compensation and xN bonding configurations, is for PLL feedback compensation, the bonded interface is broken down into smaller groups of 6 bonded channels within a transceiver bank. A PLL within each transceiver bank (ATX PLL or fPLL) is used as a transmit PLL. All the transmit PLLs share the same input reference clock.

In xN bonding configurations, one PLL is used for each bonded group. In PLL feedback compensation bonding, one PLL is used for each transceiver bank that the bonded group spans. There are no data rate limitations in PLL feedback compensation bonding, other than the natural data rate limitations of the transceiver channel and the PLL.

For feedback compensation bonding, the low-speed parallel clock must be the same frequency as the reference clock for the PLL.

fPLL Driving the Core

The fPLL can be used to drive the FPGA fabric. To ensure phase alignment between the input reference clock and the fPLL output clock, the fPLL needs to be configured in integer mode. Refer to the following figures when doing dynamic reconfiguration.

Figure 189.  Fractional and not Phase Aligned
Figure 190. Integer and Phase Aligned
Figure 191. Integer Mode phase aligned and external feedback
You must recalibrate the fPLL when you enable the phase alignment option.
  1. Modify the fPLL IP to enable fPLL reconfiguration
    • Under the Dynamic Reconfiguration Tab, turn ON Enable dynamic reconfiguration.
  2. Create logics in the core to perform following steps:
    • Read-Modify-Write 0x1 to offset address 0x126[0] of the fPLL to select internal feedback.
    • Read-Modify-Write 0x1 to offset address 0x100 of the fPLL, then Read-Modify-Write 0x1 to offset address 0x000 of the fPLL to request PreSICE to recalibrate the fPLL.
    • Monitor bit 1 of offset address of 0x280 of the fPLL and wait until this bit changes to zero. This indicates recalibration is completed. Ensure the fPLL achieves lock.
    • Read-Modify-Write 0x0 to offset address 0x126[0] of the fPLL to select the external feedback path.
  3. Monitor the fPLL lock signal, wait until the fPLL achieves lock.

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