Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents

3.2. Input Reference Clock Sources

The transmitter PLL and the clock data recovery (CDR) block need an input reference clock source to generate the clocks required for transceiver operation. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations.

Arria 10 transceiver PLLs have five possible input reference clock sources, depending on jitter requirements:

  • Dedicated reference clock pins
  • Reference clock network
  • The output of another fPLL with PLL cascading 59
  • Receiver input pins
  • Global clock or core clock 59

For the best jitter performance, Intel recommends placing the reference clock as close as possible, to the transmit PLL. For protocol jitter compliance at data rates > 10 Gbps, place the reference clock pin in the same triplet as the transmit PLL.

The following protocols require the reference clock to be placed in same bank as the transmit PLL:
  • OTU2e, OTU2, OC-192 and 10G PON
  • 6G and 12G SDI

Sourcing a reference clock from a cascaded PLL output, global clock or core clock network introduces additional jitter to transmit PLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria® 10 PLL reference clock?" for more details.

For optimum performance of GT channel, the reference clock of transmit PLL is recommended to be from a dedicated reference clock pin in the same bank.

Figure 173. Input Reference Clock Sources
  • In Arria 10 devices, the FPGA fabric core clock network can be used as an input reference source for any PLL type.
  • To successfully complete the calibration process, the reference clocks driving the PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of FPGA configuration. Otherwise, recalibration is necessary.
59 Not available for CMU.

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