Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents
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3.2. Input Reference Clock Sources

The transmitter PLL and the clock data recovery (CDR) block need an input reference clock source to generate the clocks required for transceiver operation. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations.

Arria 10 transceiver PLLs have five possible input reference clock sources, depending on jitter requirements:

  • Dedicated reference clock pins
  • Reference clock network
  • The output of another fPLL with PLL cascading 57
  • Receiver input pins
  • Global clock or core clock 57

For the