Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents

2.6.4. 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core

The Ethernet standard comprises many different PHY standards with variations in signal transmission medium and data rates.

The 1G/10Gbps Ethernet PHY IP core targets the reconfigurable 10-Mbps/100-Mbps/1-Gbps/10-Gbps data rates with one core dynamically. This Ethernet PHY interfaces to 1G/10GbE dual speed SFP+ pluggable modules, 10MB–10GbE 10GBASE-T, and 10MB/100MB/1000MB 1000BASE-T copper external PHY devices to drive CAT-6/7 shielded twisted pair cables, and chip-to-chip interfaces.

The 1G/10 Gbps Ethernet PHY (1G/10GbE ) IP function allows you to support the following features of Ethernet standards:

  • 1 GbE protocol as defined in Clause 36 of the IEEE 802.3-2008 Standard
  • GMII to connect the PHY with a media access control (MAC) as defined in Clause 35 of the IEEE 802.3-2008 Standard
  • Gigabit Ethernet Auto-negotiation as defined in Clause 37 of the IEEE 802.3-2008 Standard
  • 10GBASE-R Ethernet protocol as defined in Clause 49 of the IEEE 802.3-2008 Standard
  • Single data rate (64 data bits and 8 control bits) XGMII to provide simple and inexpensive interconnection between the MAC and the PHY as defined in Clause 46 of the IEEE 802.3-2008 Standard
  • SGMII 10-Mbps/100-Mbps/1-Gbps data rate where 10-Mbps/100-Mbps MII to connect physical media with the MAC as defined in Clause 22 of the IEEE 802.3-2008 Standard
  • Forward Error correction(FEC) as defined in Clause 74 of the IEEE 802.3-2008 Standard
  • Precision time protocol (PTP) as defined in the IEEE 1588 Standard

The 1G/10Gbps Ethernet PHY IP Core allows you to implement the 1GbE protocol using the Standard PCS and to implement the 10GbE protocol using Enhanced PCS and PMA. You can switch dynamically between the 1G and 10G data rates using dynamic reconfiguration to reprogram the core. Or, you can use the speed detection option to automatically switch data rates based on received data.

Figure 72. Top Level Modules of the 1G/10GbE PHY IP FunctionThe Enhanced PCS receives and transmits XGMII data. The Standard PCS receives and transmits GMII data.

For more information about clock and reset signal descriptions, refer to Clock and Reset Interfaces.

An Avalon® memory-mapped interface slave provides access to the 1G/10GbE PHY IP Core registers. These registers control many of the functions of the other blocks. Many of these bits are defined in Clause 45 of IEEE 802.3ap-2008 Standard.

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