Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.6.5.5.8. Avalon® Memory-Mapped Interface Signals

The Avalon® memory-mapped interface is an Avalon® memory-mapped interface slave port. This interface uses word addressing and provides access to the 16-bit configuration registers of the PHY.

Table 167.   Avalon® Memory-Mapped Interface Signals
Signal Name Direction Width Description
csr_address Input 5, 11
Use this bus to specify the register address to read from or write to. The width is:
  • 5 bits for 2.5G and 1G/2.5G configurations.
  • 11 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.
csr_read Input 1

Assert this signal to request a read operation.

csr_readdata Output 16, 32
Data read from the specified register. The data is valid only when the csr_waitrequest signal is deasserted. The width is:
  • 16 bits for 2.5G and 1G/2.5G configurations.
  • 32 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations. The upper 16 bits are reserved.
csr_write Input 1

Assert this signal to request a write operation.

csr_writedata Input 16, 32
Data to be written to the specified register. The data is written only when the csr_waitrequest signal is deasserted. The width is:
  • 16 bits for 2.5G and 1G/2.5G configurations.
  • 32 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations. The upper 16 bits are reserved.
csr_waitrequest Output 1

When asserted, indicates that the PHY is busy and not ready to accept any read or write requests.

  • When you have requested for a read or write, keep the control signals to the Avalon® memory-mapped interface constant while this signal is asserted. The request is complete when it is deasserted.
  • This signal can be high or low during idle cycles and reset. Therefore, the user application must not make any assumption of its assertion state during these periods.

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