Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.9.2.5. RX Bit Reversal

The RX bit reversal feature can be enabled in low latency, basic, and basic rate match mode. The word aligner is available in any mode, bit slip, manual, or synchronous state machine.

To enable this feature, select the Enable RX bit reversal and Enable rx_std_bitrev_ena port options. This adds rx_std_bitrev_ena. If there is more than one channel in the design, rx_std_bitrev_ena becomes a bus in which each bit corresponds to a channel. As long as rx_std_bitrev_ena is asserted, the RX data received by the core shows bit reversal.

You can verify this feature by monitoring rx_parallel_data.

Figure 142. RX Bit Reversal


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