Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Public
Document Table of Contents

6.15. Embedded Debug Features

Note: For details on TTK usage refer to the Debugging Transceiver Toolkit chapter.

The Arria® 10 Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores provide the following optional debug features to facilitate embedded test and debug capability:

  • Native PHY Debug Master Endpoint (NPDME)
  • Optional Reconfiguration Logic