Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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6.15. Embedded Debug Features

Note: For details on TTK usage refer to the Debugging Transceiver Toolkit chapter.

The Arria® 10 Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores provide the following optional debug features to facilitate embedded test and debug capability:

  • Native PHY Debug Master Endpoint (NPDME)
  • Optional Reconfiguration Logic

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