Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

2.10. Simulating the Transceiver Native PHY IP Core

Use simulation to verify the Native PHY transceiver functionality. The Quartus® Prime software supports register transfer level (RTL) and gate-level simulation in both ModelSim® - Intel FPGA Edition and third-party simulators. You run simulations using your Quartus Prime project files.

The following simulation flows are available: