Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

5.2.1.5. Pattern Generators

The Arria 10 transceivers contain hardened generators and checkers to provide a simple and easy way to verify and characterize high speed links. Hardening the pattern generators and checkers save FPGA core logic resources. The following pattern generator blocks are supported in Arria 10:
  • Pseudo Random Binary Sequence (PRBS)
  • Pseudo Random Pattern (PRP)
Note: The pattern generators and checkers are supported for non-bonded channels only.

The pattern generators or checkers are enabled by writing to the respective register bits of the Transceiver. Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for configuration details.

Did you find the information on this page useful?

Characters remaining:

Feedback Message